Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #ifndef _UAPI_TEGRA_DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define _UAPI_TEGRA_DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct drm_tegra_gem_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	 * @size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	 * The size, in bytes, of the buffer object to be created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	__u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	 * @flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	 * A bitmask of flags that influence the creation of GEM objects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	 * DRM_TEGRA_GEM_CREATE_TILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 *   Use the 16x16 tiling format for this buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 * DRM_TEGRA_GEM_CREATE_BOTTOM_UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 *   The buffer has a bottom-up layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	__u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * @handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * The handle of the created GEM object. Set by the kernel upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * successful completion of the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct drm_tegra_gem_mmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * @handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * Handle of the GEM object to obtain an mmap offset for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * @pad:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 * Structure padding that may be used in the future. Must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	__u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * @offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 * The mmap offset for the given GEM object. Set by the kernel upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 * successful completion of the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	__u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) struct drm_tegra_syncpt_read {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 * @id:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * ID of the syncpoint to read the current value from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	__u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * @value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 * The current syncpoint value. Set by the kernel upon successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 * completion of the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	__u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct drm_tegra_syncpt_incr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * @id:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * ID of the syncpoint to increment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	__u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 * @pad:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * Structure padding that may be used in the future. Must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	__u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct drm_tegra_syncpt_wait {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * @id:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 * ID of the syncpoint to wait on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	__u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * @thresh:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * Threshold value for which to wait.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	__u32 thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * @timeout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * Timeout, in milliseconds, to wait.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	__u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * @value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 * The new syncpoint value after the wait. Set by the kernel upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * successful completion of the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	__u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DRM_TEGRA_NO_TIMEOUT	(0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * struct drm_tegra_open_channel - parameters for the open channel IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct drm_tegra_open_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * @client:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 * The client ID for this channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	__u32 client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 * @pad:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 * Structure padding that may be used in the future. Must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 * @context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * The application context of this channel. Set by the kernel upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * successful completion of the IOCTL. This context needs to be passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	__u64 context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * struct drm_tegra_close_channel - parameters for the close channel IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct drm_tegra_close_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * @context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * The application context of this channel. This is obtained from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 * DRM_TEGRA_OPEN_CHANNEL IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	__u64 context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct drm_tegra_get_syncpt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 * @context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * The application context identifying the channel for which to obtain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * the syncpoint ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	__u64 context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	 * @index:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 * Index of the client syncpoint for which to obtain the ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	__u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * @id:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * The ID of the given syncpoint. Set by the kernel upon successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * completion of the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	__u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct drm_tegra_get_syncpt_base {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 * @context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 * The application context identifying for which channel to obtain the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 * wait base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	__u64 context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 * @syncpt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 * ID of the syncpoint for which to obtain the wait base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	__u32 syncpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 * @id:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	 * The ID of the wait base corresponding to the client syncpoint. Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	 * by the kernel upon successful completion of the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	__u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  * struct drm_tegra_syncpt - syncpoint increment operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct drm_tegra_syncpt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 * @id:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	 * ID of the syncpoint to operate on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	__u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 * @incrs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 * Number of increments to perform for the syncpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	__u32 incrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * struct drm_tegra_cmdbuf - structure describing a command buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct drm_tegra_cmdbuf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	 * @handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	 * Handle to a GEM object containing the command buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 * @offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 * Offset, in bytes, into the GEM object identified by @handle at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	 * which the command buffer starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	__u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	 * @words:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	 * Number of 32-bit words in this command buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	__u32 words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	 * @pad:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	 * Structure padding that may be used in the future. Must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	__u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  * struct drm_tegra_reloc - GEM object relocation structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct drm_tegra_reloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		 * @cmdbuf.handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		 * Handle to the GEM object containing the command buffer for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		 * which to perform this GEM object relocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		 * @cmdbuf.offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		 * Offset, in bytes, into the command buffer at which to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		 * insert the relocated address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		__u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	} cmdbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		 * @target.handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		 * Handle to the GEM object to be relocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		 * @target.offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		 * Offset, in bytes, into the target GEM object at which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		 * relocated data starts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		__u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	} target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	 * @shift:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	 * The number of bits by which to shift relocated addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	__u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	 * @pad:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 * Structure padding that may be used in the future. Must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	__u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)  * struct drm_tegra_waitchk - wait check structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct drm_tegra_waitchk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	 * @handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	 * Handle to the GEM object containing a command stream on which to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	 * perform the wait check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	 * @offset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	 * Offset, in bytes, of the location in the command stream to perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	 * the wait check on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	__u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	 * @syncpt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	 * ID of the syncpoint to wait check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	__u32 syncpt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	 * @thresh:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	 * Threshold value for which to check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	__u32 thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)  * struct drm_tegra_submit - job submission structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct drm_tegra_submit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	 * @context:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	 * The application context identifying the channel to use for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	 * execution of this job.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	__u64 context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	 * @num_syncpts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	 * The number of syncpoints operated on by this job. This defines the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	 * length of the array pointed to by @syncpts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	__u32 num_syncpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	 * @num_cmdbufs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	 * The number of command buffers to execute as part of this job. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	 * defines the length of the array pointed to by @cmdbufs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	__u32 num_cmdbufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	 * @num_relocs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	 * The number of relocations to perform before executing this job.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	 * This defines the length of the array pointed to by @relocs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	__u32 num_relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	 * @num_waitchks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	 * The number of wait checks to perform as part of this job. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	 * defines the length of the array pointed to by @waitchks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	__u32 num_waitchks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	 * @waitchk_mask:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	 * Bitmask of valid wait checks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	__u32 waitchk_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	 * @timeout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	 * Timeout, in milliseconds, before this job is cancelled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	__u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	 * @syncpts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	 * A pointer to an array of &struct drm_tegra_syncpt structures that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	 * specify the syncpoint operations performed as part of this job.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	 * The number of elements in the array must be equal to the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	 * given by @num_syncpts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	__u64 syncpts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	 * @cmdbufs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	 * A pointer to an array of &struct drm_tegra_cmdbuf structures that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	 * define the command buffers to execute as part of this job. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	 * number of elements in the array must be equal to the value given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	 * by @num_syncpts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	__u64 cmdbufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	 * @relocs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	 * A pointer to an array of &struct drm_tegra_reloc structures that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	 * specify the relocations that need to be performed before executing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	 * this job. The number of elements in the array must be equal to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	 * value given by @num_relocs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	__u64 relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	 * @waitchks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	 * A pointer to an array of &struct drm_tegra_waitchk structures that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	 * specify the wait checks to be performed while executing this job.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	 * The number of elements in the array must be equal to the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	 * given by @num_waitchks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	__u64 waitchks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	 * @fence:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	 * The threshold of the syncpoint associated with this job after it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	 * has been completed. Set by the kernel upon successful completion of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	 * the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	 * wait for this job to be finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	__u32 fence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	 * @reserved:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	 * This field is reserved for future use. Must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	__u32 reserved[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define DRM_TEGRA_GEM_TILING_MODE_TILED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)  * struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct drm_tegra_gem_set_tiling {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	 * @handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	 * Handle to the GEM object for which to set the tiling parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	 * @mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	 * The tiling mode to set. Must be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	 * DRM_TEGRA_GEM_TILING_MODE_PITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	 *   pitch linear format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	 * DRM_TEGRA_GEM_TILING_MODE_TILED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	 *   16x16 tiling format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	 * DRM_TEGRA_GEM_TILING_MODE_BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	 *   16Bx2 tiling format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	__u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	 * @value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	 * The value to set for the tiling mode parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	__u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	 * @pad:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	 * Structure padding that may be used in the future. Must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	__u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)  * struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct drm_tegra_gem_get_tiling {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	 * @handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	 * Handle to the GEM object for which to query the tiling parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	 * @mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	 * The tiling mode currently associated with the GEM object. Set by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	 * the kernel upon successful completion of the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	__u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	 * @value:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	 * The tiling mode parameter currently associated with the GEM object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	 * Set by the kernel upon successful completion of the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	__u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	 * @pad:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	 * Structure padding that may be used in the future. Must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	__u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define DRM_TEGRA_GEM_BOTTOM_UP		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define DRM_TEGRA_GEM_FLAGS		(DRM_TEGRA_GEM_BOTTOM_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)  * struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct drm_tegra_gem_set_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	 * @handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	 * Handle to the GEM object for which to set the flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	 * @flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 	 * The flags to set for the GEM object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	__u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)  * struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct drm_tegra_gem_get_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	 * @handle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 	 * Handle to the GEM object for which to query the flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	 * @flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	 * The flags currently associated with the GEM object. Set by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 	 * kernel upon successful completion of the IOCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	__u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define DRM_TEGRA_GEM_CREATE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define DRM_TEGRA_GEM_MMAP		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define DRM_TEGRA_SYNCPT_READ		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define DRM_TEGRA_SYNCPT_INCR		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define DRM_TEGRA_SYNCPT_WAIT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define DRM_TEGRA_OPEN_CHANNEL		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define DRM_TEGRA_CLOSE_CHANNEL		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define DRM_TEGRA_GET_SYNCPT		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define DRM_TEGRA_SUBMIT		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define DRM_TEGRA_GET_SYNCPT_BASE	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define DRM_TEGRA_GEM_SET_TILING	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define DRM_TEGRA_GEM_GET_TILING	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define DRM_TEGRA_GEM_SET_FLAGS		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define DRM_TEGRA_GEM_GET_FLAGS		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #endif