Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* savage_drm.h -- Public header for the savage driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2004  Felix Kuehling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * the rights to use, copy, modify, merge, publish, distribute, sub license,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * The above copyright notice and this permission notice (including the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * next paragraph) shall be included in all copies or substantial portions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #ifndef __SAVAGE_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define __SAVAGE_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #ifndef __SAVAGE_SAREA_DEFINES__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define __SAVAGE_SAREA_DEFINES__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* 2 heaps (1 for card, 1 for agp), each divided into up to 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * regions, subject to a minimum region size of (1<<16) == 64k.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * Clients may subdivide regions internally, but when sharing between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * clients, the region size is the minimum granularity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SAVAGE_CARD_HEAP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SAVAGE_AGP_HEAP			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SAVAGE_NR_TEX_HEAPS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SAVAGE_NR_TEX_REGIONS		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SAVAGE_LOG_MIN_TEX_REGION_SIZE	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #endif				/* __SAVAGE_SAREA_DEFINES__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) typedef struct _drm_savage_sarea {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/* LRU lists for texture memory in agp space and on the card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 						      1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/* Mechanism to validate card state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int ctxOwner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) } drm_savage_sarea_t, *drm_savage_sarea_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* Savage-specific ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DRM_SAVAGE_BCI_INIT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DRM_SAVAGE_BCI_CMDBUF           0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DRM_SAVAGE_BCI_EVENT_EMIT	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DRM_SAVAGE_BCI_EVENT_WAIT	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DRM_IOCTL_SAVAGE_BCI_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DRM_IOCTL_SAVAGE_BCI_CMDBUF		DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT	DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT	DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SAVAGE_DMA_PCI	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SAVAGE_DMA_AGP	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) typedef struct drm_savage_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		SAVAGE_INIT_BCI = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		SAVAGE_CLEANUP_BCI = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	} func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	unsigned int sarea_priv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* some parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned int cob_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned int bci_threshold_lo, bci_threshold_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned int dma_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/* frame buffer layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned int fb_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unsigned int front_offset, front_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned int back_offset, back_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	unsigned int depth_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned int depth_offset, depth_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* local textures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned int texture_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned int texture_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* physical locations of non-permanent maps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned long status_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned long buffers_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	unsigned long agp_textures_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned long cmd_dma_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } drm_savage_init_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) typedef struct drm_savage_cmdbuf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* command buffer in client's address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	drm_savage_cmd_header_t __user *cmd_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	unsigned int size;	/* size of the command buffer in 64bit units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned int dma_idx;	/* DMA buffer index to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int discard;		/* discard DMA buffer when done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* vertex buffer in client's address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned int __user *vb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned int vb_size;	/* size of client vertex buffer in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned int vb_stride;	/* stride of vertices in 32bit words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* boxes in client's address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct drm_clip_rect __user *box_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	unsigned int nbox;	/* number of clipping boxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } drm_savage_cmdbuf_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SAVAGE_WAIT_2D  0x1	/* wait for 2D idle before updating event tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SAVAGE_WAIT_3D  0x2	/* wait for 3D idle before updating event tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SAVAGE_WAIT_IRQ 0x4	/* emit or wait for IRQ, not implemented yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) typedef struct drm_savage_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } drm_savage_event_emit_t, drm_savage_event_wait_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Commands for the cmdbuf ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SAVAGE_CMD_STATE	0	/* a range of state registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SAVAGE_CMD_DMA_PRIM	1	/* vertices from DMA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SAVAGE_CMD_VB_PRIM	2	/* vertices from client vertex buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SAVAGE_CMD_DMA_IDX	3	/* indexed vertices from DMA buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SAVAGE_CMD_VB_IDX	4	/* indexed vertices client vertex buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SAVAGE_CMD_CLEAR	5	/* clear buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SAVAGE_CMD_SWAP		6	/* swap buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Primitive types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SAVAGE_PRIM_TRILIST	0	/* triangle list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SAVAGE_PRIM_TRISTRIP	1	/* triangle strip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SAVAGE_PRIM_TRIFAN	2	/* triangle fan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SAVAGE_PRIM_TRILIST_201	3	/* reorder verts for correct flat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 					 * shading on s3d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Skip flags (vertex format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SAVAGE_SKIP_Z		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SAVAGE_SKIP_W		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SAVAGE_SKIP_C0		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SAVAGE_SKIP_C1		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SAVAGE_SKIP_S0		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SAVAGE_SKIP_T0		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SAVAGE_SKIP_ST0		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SAVAGE_SKIP_S1		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SAVAGE_SKIP_T1		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SAVAGE_SKIP_ST1		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SAVAGE_SKIP_ALL_S3D	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SAVAGE_SKIP_ALL_S4	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Buffer names for clear command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SAVAGE_FRONT		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SAVAGE_BACK		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SAVAGE_DEPTH		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* 64-bit command header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) union drm_savage_cmd_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		unsigned char cmd;	/* command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		unsigned char pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		unsigned short pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		unsigned short pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		unsigned short pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	} cmd;			/* generic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		unsigned char cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		unsigned char global;	/* need idle engine? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		unsigned short count;	/* number of consecutive registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		unsigned short start;	/* first register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		unsigned short pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	} state;		/* SAVAGE_CMD_STATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		unsigned char cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		unsigned char prim;	/* primitive type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		unsigned short skip;	/* vertex format (skip flags) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		unsigned short count;	/* number of vertices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		unsigned short start;	/* first vertex in DMA/vertex buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	} prim;			/* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		unsigned char cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		unsigned char prim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		unsigned short skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		unsigned short count;	/* number of indices that follow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		unsigned short pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	} idx;			/* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		unsigned char cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		unsigned char pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		unsigned short pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	} clear0;		/* SAVAGE_CMD_CLEAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	} clear1;		/* SAVAGE_CMD_CLEAR data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif