^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Mark Yao <yzq@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * base on exynos_drm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef _UAPI_ROCKCHIP_DRM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define _UAPI_ROCKCHIP_DRM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <drm/drm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <drm/drm_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Send vcnt event instead of blocking,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * like _DRM_VBLANK_EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define _DRM_ROCKCHIP_VCNT_EVENT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRM_EVENT_ROCKCHIP_CRTC_VCNT 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* memory type definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum drm_rockchip_gem_mem_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Physically Continuous memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ROCKCHIP_BO_CONTIG = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* cachable mapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ROCKCHIP_BO_CACHABLE = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* write-combine mapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ROCKCHIP_BO_WC = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ROCKCHIP_BO_SECURE = 1 << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* keep kmap for cma buffer or alloc kmap for other type memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ROCKCHIP_BO_ALLOC_KMAP = 1 << 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* alloc page with gfp_dma32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ROCKCHIP_BO_DMA32 = 1 << 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ROCKCHIP_BO_MASK = ROCKCHIP_BO_CONTIG | ROCKCHIP_BO_CACHABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ROCKCHIP_BO_WC | ROCKCHIP_BO_SECURE | ROCKCHIP_BO_ALLOC_KMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ROCKCHIP_BO_DMA32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * User-desired buffer creation information structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @size: user-desired memory allocation size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @flags: user request for setting memory type or cache attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @handle: returned a handle to created gem object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * - this handle will be set by gem module of kernel side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct drm_rockchip_gem_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) uint64_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) uint32_t flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct drm_rockchip_gem_phys {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) uint32_t phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * A structure for getting buffer offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @handle: a pointer to gem object created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @pad: just padding to be 64-bit aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @offset: relatived offset value of the memory region allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * - this value should be set by user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct drm_rockchip_gem_map_off {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) uint32_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) uint32_t pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) uint64_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* acquire type definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum drm_rockchip_gem_cpu_acquire_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DRM_ROCKCHIP_GEM_CPU_ACQUIRE_SHARED = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DRM_ROCKCHIP_GEM_CPU_ACQUIRE_EXCLUSIVE = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum rockchip_crtc_feture {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ROCKCHIP_DRM_CRTC_FEATURE_HDR10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum rockchip_plane_feture {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ROCKCHIP_DRM_PLANE_FEATURE_SCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ROCKCHIP_DRM_PLANE_FEATURE_ALPHA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ROCKCHIP_DRM_PLANE_FEATURE_HDR2SDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ROCKCHIP_DRM_PLANE_FEATURE_SDR2HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ROCKCHIP_DRM_PLANE_FEATURE_AFBDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ROCKCHIP_DRM_PLANE_FEATURE_PDAF_POS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ROCKCHIP_DRM_PLANE_FEATURE_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum rockchip_cabc_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ROCKCHIP_DRM_CABC_MODE_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ROCKCHIP_DRM_CABC_MODE_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ROCKCHIP_DRM_CABC_MODE_LOWPOWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ROCKCHIP_DRM_CABC_MODE_USERSPACE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct drm_rockchip_vcnt_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct drm_pending_event base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DRM_ROCKCHIP_GEM_CREATE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DRM_ROCKCHIP_GEM_CPU_ACQUIRE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DRM_ROCKCHIP_GEM_CPU_RELEASE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DRM_ROCKCHIP_GEM_GET_PHYS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DRM_ROCKCHIP_GET_VCNT_EVENT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DRM_IOCTL_ROCKCHIP_GEM_CPU_ACQUIRE DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DRM_ROCKCHIP_GEM_CPU_ACQUIRE, struct drm_rockchip_gem_cpu_acquire)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DRM_IOCTL_ROCKCHIP_GEM_CPU_RELEASE DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DRM_ROCKCHIP_GEM_CPU_RELEASE, struct drm_rockchip_gem_cpu_release)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DRM_IOCTL_ROCKCHIP_GEM_GET_PHYS DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DRM_ROCKCHIP_GEM_GET_PHYS, struct drm_rockchip_gem_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DRM_IOCTL_ROCKCHIP_GET_VCNT_EVENT DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DRM_ROCKCHIP_GET_VCNT_EVENT, union drm_wait_vblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif /* _UAPI_ROCKCHIP_DRM_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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