^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The above copyright notice and this permission notice (including the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * paragraph) shall be included in all copies or substantial portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Kevin E. Martin <martin@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Gareth Hughes <gareth@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Keith Whitwell <keith@tungstengraphics.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef __RADEON_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define __RADEON_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* WARNING: If you change any of these defines, make sure to change the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * defines in the X server file (radeon_sarea.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifndef __RADEON_SAREA_DEFINES__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define __RADEON_SAREA_DEFINES__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Old style state flags, required for sarea interface (1.1 and 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * clears) and 1.2 drm_vertex2 ioctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RADEON_UPLOAD_CONTEXT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RADEON_UPLOAD_VERTFMT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RADEON_UPLOAD_LINE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RADEON_UPLOAD_BUMPMAP 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RADEON_UPLOAD_MASKS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RADEON_UPLOAD_VIEWPORT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RADEON_UPLOAD_SETUP 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RADEON_UPLOAD_TCL 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RADEON_UPLOAD_MISC 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RADEON_UPLOAD_TEX0 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RADEON_UPLOAD_TEX1 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RADEON_UPLOAD_TEX2 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RADEON_UPLOAD_TEX0IMAGES 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RADEON_UPLOAD_TEX1IMAGES 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RADEON_UPLOAD_TEX2IMAGES 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RADEON_REQUIRE_QUIESCENCE 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RADEON_UPLOAD_ALL 0x003effff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* New style per-packet identifiers for use in cmd_buffer ioctl with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * the RADEON_EMIT_PACKET command. Comments relate new packets to old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * state bits and the packet size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RADEON_EMIT_PP_MISC 0 /* context/7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RADEON_EMIT_PP_CNTL 1 /* context/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RADEON_EMIT_RE_MISC 11 /* misc/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define R200_EMIT_TFACTOR_0 30 /* tf/7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define R200_EMIT_VAP_CTL 32 /* vap/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define R200_EMIT_VTE_CNTL 48 /* vte/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define R200_EMIT_PP_CUBIC_FACES_0 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define R200_EMIT_PP_CUBIC_OFFSETS_0 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define R200_EMIT_PP_CUBIC_FACES_1 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define R200_EMIT_PP_CUBIC_OFFSETS_1 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define R200_EMIT_PP_CUBIC_FACES_2 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define R200_EMIT_PP_CUBIC_OFFSETS_2 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define R200_EMIT_PP_CUBIC_FACES_3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define R200_EMIT_PP_CUBIC_OFFSETS_3 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define R200_EMIT_PP_CUBIC_FACES_4 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define R200_EMIT_PP_CUBIC_OFFSETS_4 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define R200_EMIT_PP_CUBIC_FACES_5 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define R200_EMIT_PP_CUBIC_OFFSETS_5 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RADEON_EMIT_PP_TEX_SIZE_0 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RADEON_EMIT_PP_TEX_SIZE_1 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RADEON_EMIT_PP_TEX_SIZE_2 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define R200_EMIT_RB3D_BLENDCOLOR 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RADEON_EMIT_PP_CUBIC_FACES_0 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RADEON_EMIT_PP_CUBIC_FACES_1 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RADEON_EMIT_PP_CUBIC_FACES_2 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define R200_EMIT_PP_TRI_PERF_CNTL 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define R200_EMIT_PP_AFS_0 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define R200_EMIT_PP_AFS_1 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define R200_EMIT_ATF_TFACTOR 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define R200_EMIT_PP_TXCTLALL_0 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define R200_EMIT_PP_TXCTLALL_1 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define R200_EMIT_PP_TXCTLALL_2 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define R200_EMIT_PP_TXCTLALL_3 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define R200_EMIT_PP_TXCTLALL_4 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define R200_EMIT_PP_TXCTLALL_5 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define R200_EMIT_VAP_PVS_CNTL 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RADEON_MAX_STATE_PACKETS 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Commands understood by cmd_buffer ioctl. More can be added but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * obviously these can't be removed or changed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define RADEON_CMD_SCALARS 2 /* emit scalar data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RADEON_CMD_VECTORS 3 /* emit vector data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RADEON_CMD_PACKET3 5 /* emit hw packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * doesn't make the cpu wait, just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * the graphics hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned char cmd_type, pad0, pad1, pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned char cmd_type, packet_id, pad0, pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned char cmd_type, offset, stride, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) } scalars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned char cmd_type, offset, stride, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned char cmd_type, addr_lo, addr_hi, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } veclinear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned char cmd_type, buf_idx, pad0, pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned char cmd_type, flags, pad0, pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } drm_radeon_cmd_header_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define RADEON_WAIT_2D 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RADEON_WAIT_3D 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Allowed parameters for R300_CMD_PACKET3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define R300_CMD_PACKET3_CLEAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define R300_CMD_PACKET3_RAW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Commands understood by cmd_buffer ioctl for R300.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * The interface has not been stabilized, so some of these may be removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * and eventually reordered before stabilization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define R300_CMD_PACKET0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define R300_CMD_VPU 2 /* emit vertex program upload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define R300_CMD_PACKET3 3 /* emit a packet3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define R300_CMD_CP_DELAY 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define R300_CMD_DMA_DISCARD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define R300_CMD_WAIT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) # define R300_WAIT_2D 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) # define R300_WAIT_3D 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* these two defines are DOING IT WRONG - however
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * we have userspace which relies on using these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * The wait interface is backwards compat new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * code should use the NEW_WAIT defines below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * THESE ARE NOT BIT FIELDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) # define R300_WAIT_2D_CLEAN 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) # define R300_WAIT_3D_CLEAN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) # define R300_NEW_WAIT_2D_3D 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) # define R300_NEW_WAIT_2D_2D_CLEAN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) # define R300_NEW_WAIT_3D_3D_CLEAN 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define R300_CMD_SCRATCH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define R300_CMD_R500FP 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) typedef union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned char cmd_type, pad0, pad1, pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) } header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned char cmd_type, count, reglo, reghi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) } packet0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned char cmd_type, count, adrlo, adrhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } vpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned char cmd_type, packet, pad0, pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) } packet3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned char cmd_type, packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned short count; /* amount of packet2 to emit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned char cmd_type, buf_idx, pad0, pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned char cmd_type, flags, pad0, pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned char cmd_type, reg, n_bufs, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned char cmd_type, count, adrlo, adrhi_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } r500fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) } drm_r300_cmd_header_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define RADEON_FRONT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define RADEON_BACK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define RADEON_DEPTH 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define RADEON_STENCIL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define RADEON_CLEAR_FASTZ 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define RADEON_USE_HIERZ 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define RADEON_USE_COMP_ZBUF 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define R500FP_CONSTANT_TYPE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define R500FP_CONSTANT_CLAMP (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Primitive types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define RADEON_POINTS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define RADEON_LINES 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define RADEON_LINE_STRIP 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define RADEON_TRIANGLES 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define RADEON_TRIANGLE_FAN 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define RADEON_TRIANGLE_STRIP 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Vertex/indirect buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define RADEON_BUFFER_SIZE 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Byte offsets for indirect buffer data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define RADEON_INDEX_PRIM_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define RADEON_SCRATCH_REG_OFFSET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define R600_SCRATCH_REG_OFFSET 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define RADEON_NR_SAREA_CLIPRECTS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* There are 2 heaps (local/GART). Each region within a heap is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * minimum of 64k, and there are at most 64 of them per heap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define RADEON_LOCAL_TEX_HEAP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define RADEON_GART_TEX_HEAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define RADEON_NR_TEX_HEAPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define RADEON_NR_TEX_REGIONS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define RADEON_LOG_TEX_GRANULARITY 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define RADEON_MAX_TEXTURE_LEVELS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define RADEON_MAX_TEXTURE_UNITS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define RADEON_MAX_SURFACES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Blits have strict offset rules. All blit offset must be aligned on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * a 1K-byte boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define RADEON_OFFSET_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #endif /* __RADEON_SAREA_DEFINES__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int green;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int alpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) } radeon_color_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Context state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int pp_misc; /* 0x1c14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int pp_fog_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int re_solid_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned int rb3d_blendcntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int rb3d_depthoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int rb3d_depthpitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int rb3d_zstencilcntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int pp_cntl; /* 0x1c38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int rb3d_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int rb3d_coloroffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int re_width_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int rb3d_colorpitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int se_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Vertex format state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned int se_coord_fmt; /* 0x1c50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Line state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int re_line_pattern; /* 0x1cd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int re_line_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int se_line_width; /* 0x1db8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Bumpmap state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned int pp_lum_matrix; /* 0x1d00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int pp_rot_matrix_0; /* 0x1d58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int pp_rot_matrix_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Mask state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int rb3d_stencilrefmask; /* 0x1d7c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int rb3d_ropcntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int rb3d_planemask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Viewport state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int se_vport_xscale; /* 0x1d98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int se_vport_xoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int se_vport_yscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int se_vport_yoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int se_vport_zscale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int se_vport_zoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Setup state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int se_cntl_status; /* 0x2140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Misc state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int re_top_left; /* 0x26c0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int re_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) } drm_radeon_context_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Zbias state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int se_zbias_factor; /* 0x1dac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int se_zbias_constant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } drm_radeon_context2_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Setup registers for each texture unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int pp_txfilter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int pp_txformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int pp_txoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int pp_txcblend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int pp_txablend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int pp_tfactor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int pp_border_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) } drm_radeon_texture_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int prim:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int stateidx:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int vc_format; /* vertex format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } drm_radeon_prim_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) drm_radeon_context_regs_t context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) drm_radeon_context2_regs_t context2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } drm_radeon_state_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* The channel for communication of state information to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * kernel on firing a vertex buffer with either of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * obsoleted vertex/index ioctls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) drm_radeon_context_regs_t context_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned int dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int vertsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int vc_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* The current cliprects, or a subset thereof.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int nbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Counters for client-side throttling of rendering clients.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int last_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int last_dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int last_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int tex_age[RADEON_NR_TEX_HEAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int ctx_owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int pfState; /* number of 3d windows (0,1,2ormore) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int pfCurrentPage; /* which buffer is being displayed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int crtc2_base; /* CRTC2 frame offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int tiling_enabled; /* set by drm, read by 2d + 3d clients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) } drm_radeon_sarea_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* WARNING: If you change any of these defines, make sure to change the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * defines in the Xserver file (xf86drmRadeon.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * KW: actually it's illegal to change any of this (backwards compatibility).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Radeon specific ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * The device specific ioctl range is 0x40 to 0x79.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define DRM_RADEON_CP_INIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define DRM_RADEON_CP_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define DRM_RADEON_CP_STOP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define DRM_RADEON_CP_RESET 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define DRM_RADEON_CP_IDLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define DRM_RADEON_RESET 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define DRM_RADEON_FULLSCREEN 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define DRM_RADEON_SWAP 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define DRM_RADEON_CLEAR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define DRM_RADEON_VERTEX 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define DRM_RADEON_INDICES 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define DRM_RADEON_NOT_USED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DRM_RADEON_STIPPLE 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define DRM_RADEON_INDIRECT 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define DRM_RADEON_TEXTURE 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define DRM_RADEON_VERTEX2 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define DRM_RADEON_CMDBUF 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define DRM_RADEON_GETPARAM 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DRM_RADEON_FLIP 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define DRM_RADEON_ALLOC 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define DRM_RADEON_FREE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define DRM_RADEON_INIT_HEAP 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define DRM_RADEON_IRQ_EMIT 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define DRM_RADEON_IRQ_WAIT 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define DRM_RADEON_CP_RESUME 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define DRM_RADEON_SETPARAM 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define DRM_RADEON_SURF_ALLOC 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define DRM_RADEON_SURF_FREE 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* KMS ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define DRM_RADEON_GEM_INFO 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define DRM_RADEON_GEM_CREATE 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define DRM_RADEON_GEM_MMAP 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define DRM_RADEON_GEM_PREAD 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define DRM_RADEON_GEM_PWRITE 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define DRM_RADEON_GEM_SET_DOMAIN 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define DRM_RADEON_GEM_WAIT_IDLE 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define DRM_RADEON_CS 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define DRM_RADEON_INFO 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define DRM_RADEON_GEM_SET_TILING 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define DRM_RADEON_GEM_GET_TILING 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define DRM_RADEON_GEM_BUSY 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define DRM_RADEON_GEM_VA 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define DRM_RADEON_GEM_OP 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define DRM_RADEON_GEM_USERPTR 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* KMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) typedef struct drm_radeon_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) RADEON_INIT_CP = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) RADEON_CLEANUP_CP = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) RADEON_INIT_R200_CP = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) RADEON_INIT_R300_CP = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) RADEON_INIT_R600_CP = 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned long sarea_priv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int is_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int cp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int gart_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int usec_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int fb_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned int front_offset, front_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int back_offset, back_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int depth_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned int depth_offset, depth_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned long fb_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned long mmio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned long ring_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned long ring_rptr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned long buffers_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned long gart_textures_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } drm_radeon_init_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) typedef struct drm_radeon_cp_stop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) } drm_radeon_cp_stop_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) typedef struct drm_radeon_fullscreen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) RADEON_INIT_FULLSCREEN = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) RADEON_CLEANUP_FULLSCREEN = 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } drm_radeon_fullscreen_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define CLEAR_X1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define CLEAR_Y1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define CLEAR_X2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define CLEAR_Y2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define CLEAR_DEPTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) typedef union drm_radeon_clear_rect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) float f[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned int ui[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) } drm_radeon_clear_rect_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) typedef struct drm_radeon_clear {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned int clear_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned int clear_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) unsigned int color_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned int depth_mask; /* misnamed field: should be stencil */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) drm_radeon_clear_rect_t __user *depth_boxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } drm_radeon_clear_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) typedef struct drm_radeon_vertex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int prim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int idx; /* Index of vertex buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) int count; /* Number of vertices in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int discard; /* Client finished with buffer? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } drm_radeon_vertex_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) typedef struct drm_radeon_indices {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int prim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int discard; /* Client finished with buffer? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) } drm_radeon_indices_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * - allows multiple primitives and state changes in a single ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * - supports driver change to emit native primitives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) typedef struct drm_radeon_vertex2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int idx; /* Index of vertex buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int discard; /* Client finished with buffer? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int nr_states;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) drm_radeon_state_t __user *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int nr_prims;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) drm_radeon_prim_t __user *prim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } drm_radeon_vertex2_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* v1.3 - obsoletes drm_radeon_vertex2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * - allows arbitrarily large cliprect list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * - allows updating of tcl packet, vector and scalar state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * - allows memory-efficient description of state updates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * - allows state to be emitted without a primitive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * (for clears, ctx switches)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * - allows more than one dma buffer to be referenced per ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * - supports tcl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * - may be extended in future versions with new cmd types, packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) typedef struct drm_radeon_cmd_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int bufsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) char __user *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int nbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct drm_clip_rect __user *boxes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } drm_radeon_cmd_buffer_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) typedef struct drm_radeon_tex_image {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) unsigned int x, y; /* Blit coordinates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned int width, height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) const void __user *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } drm_radeon_tex_image_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) typedef struct drm_radeon_texture {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int width; /* Texture image coordinates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) drm_radeon_tex_image_t __user *image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) } drm_radeon_texture_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) typedef struct drm_radeon_stipple {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned int __user *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) } drm_radeon_stipple_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) typedef struct drm_radeon_indirect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } drm_radeon_indirect_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* enum for card type parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define RADEON_CARD_PCI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define RADEON_CARD_AGP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define RADEON_CARD_PCIE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* 1.3: An ioctl to get parameters that aren't available to the 3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * client any other way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define RADEON_PARAM_LAST_FRAME 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define RADEON_PARAM_LAST_DISPATCH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define RADEON_PARAM_LAST_CLEAR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* Added with DRM version 1.6. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define RADEON_PARAM_IRQ_NR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Added with DRM version 1.8. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define RADEON_PARAM_STATUS_HANDLE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define RADEON_PARAM_SAREA_HANDLE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define RADEON_PARAM_GART_TEX_HANDLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define RADEON_PARAM_SCRATCH_OFFSET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define RADEON_PARAM_CARD_TYPE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define RADEON_PARAM_FB_LOCATION 14 /* FB location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define RADEON_PARAM_DEVICE_ID 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) typedef struct drm_radeon_getparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void __user *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) } drm_radeon_getparam_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* 1.6: Set up a memory manager for regions of shared memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define RADEON_MEM_REGION_GART 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define RADEON_MEM_REGION_FB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) typedef struct drm_radeon_mem_alloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int __user *region_offset; /* offset from start of fb or GART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) } drm_radeon_mem_alloc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) typedef struct drm_radeon_mem_free {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int region_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } drm_radeon_mem_free_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) typedef struct drm_radeon_mem_init_heap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) int region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) } drm_radeon_mem_init_heap_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* 1.6: Userspace can request & wait on irq's:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) typedef struct drm_radeon_irq_emit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int __user *irq_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } drm_radeon_irq_emit_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) typedef struct drm_radeon_irq_wait {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int irq_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) } drm_radeon_irq_wait_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* 1.10: Clients tell the DRM where they think the framebuffer is located in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * the card's address space, via a new generic ioctl to set parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) typedef struct drm_radeon_setparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) unsigned int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __s64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) } drm_radeon_setparam_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* 1.14: Clients can allocate/free a surface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) typedef struct drm_radeon_surface_alloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) unsigned int address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) } drm_radeon_surface_alloc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) typedef struct drm_radeon_surface_free {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned int address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) } drm_radeon_surface_free_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define DRM_RADEON_VBLANK_CRTC1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define DRM_RADEON_VBLANK_CRTC2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * Kernel modesetting world below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define RADEON_GEM_DOMAIN_CPU 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define RADEON_GEM_DOMAIN_GTT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define RADEON_GEM_DOMAIN_VRAM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct drm_radeon_gem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) __u64 gart_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) __u64 vram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) __u64 vram_visible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define RADEON_GEM_NO_BACKING_STORE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define RADEON_GEM_GTT_UC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define RADEON_GEM_GTT_WC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* BO is expected to be accessed by the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define RADEON_GEM_CPU_ACCESS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* CPU access is not expected to work for this BO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct drm_radeon_gem_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) __u64 alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) __u32 initial_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * This is not a reliable API and you should expect it to fail for any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * number of reasons and have fallback path that do not use userptr to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * perform any operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define RADEON_GEM_USERPTR_READONLY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define RADEON_GEM_USERPTR_ANONONLY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define RADEON_GEM_USERPTR_VALIDATE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define RADEON_GEM_USERPTR_REGISTER (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct drm_radeon_gem_userptr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) __u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define RADEON_TILING_MACRO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define RADEON_TILING_MICRO 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define RADEON_TILING_SWAP_16BIT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define RADEON_TILING_SWAP_32BIT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* this object requires a surface when mapped - i.e. front buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define RADEON_TILING_SURFACE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define RADEON_TILING_MICRO_SQUARE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define RADEON_TILING_EG_BANKW_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define RADEON_TILING_EG_BANKW_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define RADEON_TILING_EG_BANKH_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define RADEON_TILING_EG_BANKH_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct drm_radeon_gem_set_tiling {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) __u32 tiling_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) __u32 pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct drm_radeon_gem_get_tiling {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) __u32 tiling_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) __u32 pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct drm_radeon_gem_mmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) __u64 addr_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct drm_radeon_gem_set_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) __u32 read_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) __u32 write_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct drm_radeon_gem_wait_idle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct drm_radeon_gem_busy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) __u32 domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct drm_radeon_gem_pread {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /** Handle for the object being read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /** Offset into the object to read from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /** Length of data to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /** Pointer to write the data into. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* void *, but pointers are not 32/64 compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) __u64 data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct drm_radeon_gem_pwrite {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /** Handle for the object being written to. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /** Offset into the object to write to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /** Length of data to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /** Pointer to read the data from. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* void *, but pointers are not 32/64 compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) __u64 data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* Sets or returns a value associated with a buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct drm_radeon_gem_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) __u32 handle; /* buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) __u32 op; /* RADEON_GEM_OP_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) __u64 value; /* input or return value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define RADEON_VA_MAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define RADEON_VA_UNMAP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define RADEON_VA_RESULT_OK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define RADEON_VA_RESULT_ERROR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define RADEON_VA_RESULT_VA_EXIST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define RADEON_VM_PAGE_VALID (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define RADEON_VM_PAGE_READABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define RADEON_VM_PAGE_WRITEABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define RADEON_VM_PAGE_SYSTEM (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define RADEON_VM_PAGE_SNOOPED (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct drm_radeon_gem_va {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) __u32 operation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) __u32 vm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define RADEON_CHUNK_ID_RELOCS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define RADEON_CHUNK_ID_IB 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define RADEON_CHUNK_ID_FLAGS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define RADEON_CHUNK_ID_CONST_IB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define RADEON_CS_KEEP_TILING_FLAGS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define RADEON_CS_USE_VM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define RADEON_CS_RING_GFX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define RADEON_CS_RING_COMPUTE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define RADEON_CS_RING_DMA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define RADEON_CS_RING_UVD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define RADEON_CS_RING_VCE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* 0 = normal, + = higher priority, - = lower priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct drm_radeon_cs_chunk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) __u32 chunk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) __u32 length_dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) __u64 chunk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* drm_radeon_cs_reloc.flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define RADEON_RELOC_PRIO_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct drm_radeon_cs_reloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) __u32 read_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) __u32 write_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct drm_radeon_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) __u32 num_chunks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) __u32 cs_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* this points to __u64 * which point to cs chunks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) __u64 chunks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* updates to the limits after this CS ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) __u64 gart_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) __u64 vram_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define RADEON_INFO_DEVICE_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define RADEON_INFO_NUM_GB_PIPES 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define RADEON_INFO_NUM_Z_PIPES 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define RADEON_INFO_ACCEL_WORKING 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define RADEON_INFO_CRTC_FROM_ID 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define RADEON_INFO_ACCEL_WORKING2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define RADEON_INFO_TILING_CONFIG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define RADEON_INFO_WANT_HYPERZ 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* virtual address start, va < start are reserved by the kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define RADEON_INFO_VA_START 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* maximum size of ib using the virtual memory cs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* max pipes - needed for compute shaders */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define RADEON_INFO_MAX_PIPES 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define RADEON_INFO_TIMESTAMP 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* max shader engines (SE) - needed for geometry shaders, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define RADEON_INFO_MAX_SE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* max SH per SE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define RADEON_INFO_MAX_SH_PER_SE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* fast fb access is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define RADEON_INFO_FASTFB_WORKING 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* query if a RADEON_CS_RING_* submission is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define RADEON_INFO_RING_WORKING 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* SI tile mode array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* query if CP DMA is supported on the compute ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* CIK macrotile mode array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* query the number of render backends */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* max engine clock - needed for OpenCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define RADEON_INFO_MAX_SCLK 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* version of VCE firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define RADEON_INFO_VCE_FW_VERSION 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* version of VCE feedback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define RADEON_INFO_VCE_FB_VERSION 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define RADEON_INFO_NUM_BYTES_MOVED 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define RADEON_INFO_VRAM_USAGE 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define RADEON_INFO_GTT_USAGE 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define RADEON_INFO_CURRENT_GPU_TEMP 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define RADEON_INFO_CURRENT_GPU_SCLK 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define RADEON_INFO_CURRENT_GPU_MCLK 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define RADEON_INFO_READ_REG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define RADEON_INFO_VA_UNMAP_WORKING 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define RADEON_INFO_GPU_RESET_COUNTER 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct drm_radeon_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) __u32 request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) __u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* Those correspond to the tile index to use, this is to explicitly state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * the API that is implicitly defined by the tile mode array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define SI_TILE_MODE_COLOR_1D 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define SI_TILE_MODE_COLOR_1D_SCANOUT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define SI_TILE_MODE_COLOR_2D_8BPP 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define SI_TILE_MODE_COLOR_2D_16BPP 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define SI_TILE_MODE_COLOR_2D_32BPP 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define SI_TILE_MODE_COLOR_2D_64BPP 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define SI_TILE_MODE_DEPTH_STENCIL_1D 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define SI_TILE_MODE_DEPTH_STENCIL_2D 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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