Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * The above copyright notice and this permission notice (including the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * paragraph) shall be included in all copies or substantial portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *    Gareth Hughes <gareth@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *    Kevin E. Martin <martin@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #ifndef __R128_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define __R128_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* WARNING: If you change any of these defines, make sure to change the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * defines in the X server file (r128_sarea.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #ifndef __R128_SAREA_DEFINES__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define __R128_SAREA_DEFINES__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* What needs to be changed for the current vertex buffer?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define R128_UPLOAD_CONTEXT		0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define R128_UPLOAD_SETUP		0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define R128_UPLOAD_TEX0		0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define R128_UPLOAD_TEX1		0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define R128_UPLOAD_TEX0IMAGES		0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define R128_UPLOAD_TEX1IMAGES		0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define R128_UPLOAD_CORE		0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define R128_UPLOAD_MASKS		0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define R128_UPLOAD_WINDOW		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define R128_UPLOAD_CLIPRECTS		0x200	/* handled client-side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define R128_REQUIRE_QUIESCENCE		0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define R128_UPLOAD_ALL			0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define R128_FRONT			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define R128_BACK			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define R128_DEPTH			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Primitive types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define R128_POINTS			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define R128_LINES			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define R128_LINE_STRIP			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define R128_TRIANGLES			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define R128_TRIANGLE_FAN		0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define R128_TRIANGLE_STRIP		0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* Vertex/indirect buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define R128_BUFFER_SIZE		16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* Byte offsets for indirect buffer data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define R128_INDEX_PRIM_OFFSET		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define R128_HOSTDATA_BLIT_OFFSET	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* Keep these small for testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define R128_NR_SAREA_CLIPRECTS		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* There are 2 heaps (local/AGP).  Each region within a heap is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  *  minimum of 64k, and there are at most 64 of them per heap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define R128_LOCAL_TEX_HEAP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define R128_AGP_TEX_HEAP		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define R128_NR_TEX_HEAPS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define R128_NR_TEX_REGIONS		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define R128_LOG_TEX_GRANULARITY	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define R128_NR_CONTEXT_REGS		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define R128_MAX_TEXTURE_LEVELS		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define R128_MAX_TEXTURE_UNITS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif				/* __R128_SAREA_DEFINES__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* Context state - can be written in one large chunk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned int dst_pitch_offset_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned int dp_gui_master_cntl_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned int sc_top_left_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned int sc_bottom_right_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned int z_offset_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned int z_pitch_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	unsigned int z_sten_cntl_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	unsigned int tex_cntl_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned int misc_3d_state_cntl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	unsigned int texture_clr_cmp_clr_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	unsigned int texture_clr_cmp_msk_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned int fog_color_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* Texture state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	unsigned int tex_size_pitch_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned int constant_color_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* Setup state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned int pm4_vc_fpu_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned int setup_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* Mask state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	unsigned int dp_write_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned int sten_ref_mask_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	unsigned int plane_3d_mask_c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Window state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	unsigned int window_xy_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* Core state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unsigned int scale_3d_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } drm_r128_context_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Setup registers for each texture unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	unsigned int tex_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	unsigned int tex_combine_cntl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned int tex_size_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	unsigned int tex_border_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } drm_r128_texture_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) typedef struct drm_r128_sarea {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* The channel for communication of state information to the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * on firing a vertex buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	drm_r128_context_regs_t context_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	unsigned int dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	unsigned int vertsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	unsigned int vc_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* The current cliprects, or a subset thereof.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned int nbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* Counters for client-side throttling of rendering clients.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned int last_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned int last_dispatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	unsigned int tex_age[R128_NR_TEX_HEAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int ctx_owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int pfAllowPageFlip;	/* number of 3d windows (0,1,2 or more) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int pfCurrentPage;	/* which buffer is being displayed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } drm_r128_sarea_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* WARNING: If you change any of these defines, make sure to change the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * defines in the Xserver file (xf86drmR128.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Rage 128 specific ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  * The device specific ioctl range is 0x40 to 0x79.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DRM_R128_INIT       0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DRM_R128_CCE_START  0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DRM_R128_CCE_STOP   0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DRM_R128_CCE_RESET  0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DRM_R128_CCE_IDLE   0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* 0x05 not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DRM_R128_RESET      0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DRM_R128_SWAP       0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DRM_R128_CLEAR      0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DRM_R128_VERTEX     0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DRM_R128_INDICES    0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DRM_R128_BLIT       0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DRM_R128_DEPTH      0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DRM_R128_STIPPLE    0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* 0x0e not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DRM_R128_INDIRECT   0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DRM_R128_FULLSCREEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DRM_R128_CLEAR2     0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DRM_R128_GETPARAM   0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DRM_R128_FLIP       0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DRM_IOCTL_R128_INIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DRM_IOCTL_R128_CCE_START  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DRM_IOCTL_R128_CCE_STOP   DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DRM_IOCTL_R128_CCE_RESET  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DRM_IOCTL_R128_CCE_IDLE   DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* 0x05 not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DRM_IOCTL_R128_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_R128_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DRM_IOCTL_R128_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_SWAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DRM_IOCTL_R128_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DRM_IOCTL_R128_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DRM_IOCTL_R128_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DRM_IOCTL_R128_BLIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DRM_IOCTL_R128_DEPTH      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DRM_IOCTL_R128_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* 0x0e not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DRM_IOCTL_R128_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DRM_IOCTL_R128_CLEAR2     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DRM_IOCTL_R128_GETPARAM   DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DRM_IOCTL_R128_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_FLIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) typedef struct drm_r128_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		R128_INIT_CCE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		R128_CLEANUP_CCE = 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	} func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	unsigned long sarea_priv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	int is_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	int cce_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	int cce_secure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	int ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	int usec_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	unsigned int fb_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	unsigned int front_offset, front_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	unsigned int back_offset, back_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	unsigned int depth_bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	unsigned int depth_offset, depth_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	unsigned int span_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	unsigned long fb_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	unsigned long mmio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	unsigned long ring_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	unsigned long ring_rptr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	unsigned long buffers_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	unsigned long agp_textures_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } drm_r128_init_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) typedef struct drm_r128_cce_stop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	int flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	int idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } drm_r128_cce_stop_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) typedef struct drm_r128_clear {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	unsigned int clear_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	unsigned int clear_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	unsigned int color_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	unsigned int depth_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) } drm_r128_clear_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) typedef struct drm_r128_vertex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int prim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	int idx;		/* Index of vertex buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	int count;		/* Number of vertices in buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int discard;		/* Client finished with buffer? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } drm_r128_vertex_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) typedef struct drm_r128_indices {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	int prim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	int end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	int discard;		/* Client finished with buffer? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) } drm_r128_indices_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) typedef struct drm_r128_blit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	int pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	unsigned short x, y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	unsigned short width, height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) } drm_r128_blit_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) typedef struct drm_r128_depth {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		R128_WRITE_SPAN = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		R128_WRITE_PIXELS = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		R128_READ_SPAN = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		R128_READ_PIXELS = 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	} func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	int __user *x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	int __user *y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	unsigned int __user *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	unsigned char __user *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) } drm_r128_depth_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) typedef struct drm_r128_stipple {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	unsigned int __user *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } drm_r128_stipple_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) typedef struct drm_r128_indirect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	int end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int discard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } drm_r128_indirect_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) typedef struct drm_r128_fullscreen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		R128_INIT_FULLSCREEN = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		R128_CLEANUP_FULLSCREEN = 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	} func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } drm_r128_fullscreen_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* 2.3: An ioctl to get parameters that aren't available to the 3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  * client any other way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define R128_PARAM_IRQ_NR            1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) typedef struct drm_r128_getparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	void __user *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } drm_r128_getparam_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif