^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2013 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The above copyright notice and this permission notice (including the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * paragraph) shall be included in all copies or substantial portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef QXL_DRM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define QXL_DRM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Please note that modifications to all structs defined here are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * subject to backwards-compatibility constraints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * compatibility Keep fields aligned to their size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QXL_GEM_DOMAIN_CPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define QXL_GEM_DOMAIN_VRAM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define QXL_GEM_DOMAIN_SURFACE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRM_QXL_ALLOC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRM_QXL_MAP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRM_QXL_EXECBUFFER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRM_QXL_UPDATE_AREA 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRM_QXL_GETPARAM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRM_QXL_CLIENTCAP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRM_QXL_ALLOC_SURF 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct drm_qxl_alloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __u32 handle; /* 0 is an invalid handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct drm_qxl_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __u64 offset; /* use for mmap system call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * dest is the bo we are writing the relocation into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * src is bo we are relocating.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * *(dest_handle.base_addr + dest_offset) = physical_address(src_handle.addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * src_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QXL_RELOC_TYPE_BO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define QXL_RELOC_TYPE_SURF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct drm_qxl_reloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __u64 src_offset; /* offset into src_handle or src buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __u64 dst_offset; /* offset in dest handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __u32 src_handle; /* dest handle to compute address from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __u32 dst_handle; /* 0 if to command buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __u32 reloc_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct drm_qxl_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __u64 command; /* void* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __u64 relocs; /* struct drm_qxl_reloc* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __u32 command_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __u32 relocs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct drm_qxl_execbuffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __u32 flags; /* for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __u32 commands_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __u64 commands; /* struct drm_qxl_command* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct drm_qxl_update_area {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __u32 top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __u32 left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __u32 bottom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __u32 right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QXL_PARAM_MAX_RELOCS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct drm_qxl_getparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __u64 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* these are one bit values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct drm_qxl_clientcap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct drm_qxl_alloc_surf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __u32 format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __s32 stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DRM_IOCTL_QXL_ALLOC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC, struct drm_qxl_alloc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DRM_IOCTL_QXL_MAP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_MAP, struct drm_qxl_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DRM_IOCTL_QXL_EXECBUFFER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_EXECBUFFER,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct drm_qxl_execbuffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DRM_IOCTL_QXL_UPDATE_AREA \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_UPDATE_AREA,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct drm_qxl_update_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DRM_IOCTL_QXL_GETPARAM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_GETPARAM,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct drm_qxl_getparam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DRM_IOCTL_QXL_CLIENTCAP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DRM_IOW(DRM_COMMAND_BASE + DRM_QXL_CLIENTCAP,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct drm_qxl_clientcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DRM_IOCTL_QXL_ALLOC_SURF \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DRM_IOWR(DRM_COMMAND_BASE + DRM_QXL_ALLOC_SURF,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct drm_qxl_alloc_surf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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