^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * include/uapi/drm/omap_drm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Rob Clark <rob@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * under the terms of the GNU General Public License version 2 as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This program is distributed in the hope that it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * You should have received a copy of the GNU General Public License along with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * this program. If not, see <http://www.gnu.org/licenses/>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifndef __OMAP_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define __OMAP_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Please note that modifications to all structs defined here are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * subject to backwards-compatibility constraints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP_PARAM_CHIPSET_ID 1 /* ie. 0x3430, 0x4430, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct drm_omap_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __u64 param; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) __u64 value; /* in (set_param), out (get_param) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Scanout buffer, consumable by DSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP_BO_SCANOUT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Buffer CPU caching mode: cached, write-combining or uncached. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP_BO_CACHED 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP_BO_WC 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP_BO_UNCACHED 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP_BO_CACHE_MASK 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Use TILER for the buffer. The TILER container unit can be 8, 16 or 32 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP_BO_TILED_8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP_BO_TILED_16 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP_BO_TILED_32 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP_BO_TILED_MASK 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) union omap_gem_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __u32 bytes; /* (for non-tiled formats) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } tiled; /* (for tiled formats) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct drm_omap_gem_new {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) union omap_gem_size size; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __u32 flags; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __u32 handle; /* out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __u32 __pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* mask of operations: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum omap_gem_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) OMAP_GEM_READ = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) OMAP_GEM_WRITE = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct drm_omap_gem_cpu_prep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __u32 handle; /* buffer handle (in) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __u32 op; /* mask of omap_gem_op (in) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct drm_omap_gem_cpu_fini {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __u32 handle; /* buffer handle (in) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __u32 op; /* mask of omap_gem_op (in) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* TODO maybe here we pass down info about what regions are touched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * by sw so we can be clever about cache ops? For now a placeholder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * set to zero and we just do full buffer flush..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __u32 nregions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __u32 __pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct drm_omap_gem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __u32 handle; /* buffer handle (in) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __u64 offset; /* mmap offset (out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* note: in case of tiled buffers, the user virtual size can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * different from the physical size (ie. how many pages are needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * to back the object) which is returned in DRM_IOCTL_GEM_OPEN..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * This size here is the one that should be used if you want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * mmap() the buffer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __u32 size; /* virtual size for mmap'ing (out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __u32 __pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DRM_OMAP_GET_PARAM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DRM_OMAP_SET_PARAM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DRM_OMAP_GEM_NEW 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DRM_OMAP_GEM_CPU_PREP 0x04 /* Deprecated, to be removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DRM_OMAP_GEM_CPU_FINI 0x05 /* Deprecated, to be removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DRM_OMAP_GEM_INFO 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DRM_OMAP_NUM_IOCTLS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DRM_IOCTL_OMAP_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_PARAM, struct drm_omap_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DRM_IOCTL_OMAP_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_SET_PARAM, struct drm_omap_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DRM_IOCTL_OMAP_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_NEW, struct drm_omap_gem_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DRM_IOCTL_OMAP_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_PREP, struct drm_omap_gem_cpu_prep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DRM_IOCTL_OMAP_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, struct drm_omap_gem_cpu_fini)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DRM_IOCTL_OMAP_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_INFO, struct drm_omap_gem_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif /* __OMAP_DRM_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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