Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright 2005 Stephane Marchesin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * The above copyright notice and this permission notice (including the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * paragraph) shall be included in all copies or substantial portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #ifndef __NOUVEAU_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define __NOUVEAU_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DRM_NOUVEAU_EVENT_NVIF                                       0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define NOUVEAU_GEM_DOMAIN_COHERENT  (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define NOUVEAU_GEM_TILE_COMP        0x00030000 /* nv50-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define NOUVEAU_GEM_TILE_16BPP       0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define NOUVEAU_GEM_TILE_32BPP       0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define NOUVEAU_GEM_TILE_ZETA        0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct drm_nouveau_gem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	__u32 domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	__u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	__u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	__u64 map_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	__u32 tile_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	__u32 tile_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct drm_nouveau_gem_new {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	struct drm_nouveau_gem_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	__u32 channel_hint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	__u32 align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define NOUVEAU_GEM_MAX_BUFFERS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) struct drm_nouveau_gem_pushbuf_bo_presumed {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	__u32 valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	__u32 domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	__u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) struct drm_nouveau_gem_pushbuf_bo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	__u64 user_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	__u32 read_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__u32 write_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	__u32 valid_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define NOUVEAU_GEM_RELOC_OR   (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define NOUVEAU_GEM_MAX_RELOCS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) struct drm_nouveau_gem_pushbuf_reloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	__u32 reloc_bo_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	__u32 reloc_bo_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	__u32 bo_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	__u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	__u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	__u32 vor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	__u32 tor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define NOUVEAU_GEM_MAX_PUSH 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) struct drm_nouveau_gem_pushbuf_push {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	__u32 bo_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	__u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	__u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	__u64 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct drm_nouveau_gem_pushbuf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	__u32 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	__u32 nr_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	__u64 buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	__u32 nr_relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	__u32 nr_push;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	__u64 relocs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	__u64 push;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	__u32 suffix0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	__u32 suffix1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define NOUVEAU_GEM_PUSHBUF_SYNC                                    (1ULL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	__u64 vram_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	__u64 gart_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct drm_nouveau_gem_cpu_prep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	__u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct drm_nouveau_gem_cpu_fini {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	__u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DRM_NOUVEAU_GETPARAM           0x00 /* deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DRM_NOUVEAU_SETPARAM           0x01 /* deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DRM_NOUVEAU_CHANNEL_ALLOC      0x02 /* deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DRM_NOUVEAU_CHANNEL_FREE       0x03 /* deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DRM_NOUVEAU_GROBJ_ALLOC        0x04 /* deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05 /* deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DRM_NOUVEAU_GPUOBJ_FREE        0x06 /* deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DRM_NOUVEAU_NVIF               0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DRM_NOUVEAU_SVM_INIT           0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DRM_NOUVEAU_SVM_BIND           0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DRM_NOUVEAU_GEM_NEW            0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DRM_NOUVEAU_GEM_PUSHBUF        0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DRM_NOUVEAU_GEM_CPU_PREP       0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DRM_NOUVEAU_GEM_CPU_FINI       0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DRM_NOUVEAU_GEM_INFO           0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct drm_nouveau_svm_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	__u64 unmanaged_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	__u64 unmanaged_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct drm_nouveau_svm_bind {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	__u64 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	__u64 va_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	__u64 va_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	__u64 npages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	__u64 stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	__u64 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	__u64 reserved0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	__u64 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define NOUVEAU_SVM_BIND_COMMAND_SHIFT          0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define NOUVEAU_SVM_BIND_COMMAND_BITS           8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define NOUVEAU_SVM_BIND_COMMAND_MASK           ((1 << 8) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT         8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define NOUVEAU_SVM_BIND_PRIORITY_BITS          8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define NOUVEAU_SVM_BIND_PRIORITY_MASK          ((1 << 8) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define NOUVEAU_SVM_BIND_TARGET_SHIFT           16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define NOUVEAU_SVM_BIND_TARGET_BITS            32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define NOUVEAU_SVM_BIND_TARGET_MASK            0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * Below is use to validate ioctl argument, userspace can also use it to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * sure that no bit are set beyond known fields for a given kernel version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define NOUVEAU_SVM_BIND_VALID_BITS     48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define NOUVEAU_SVM_BIND_VALID_MASK     ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  * result: number of page successfuly migrate to the target memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE               0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM               (1UL << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DRM_IOCTL_NOUVEAU_SVM_INIT           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DRM_IOCTL_NOUVEAU_SVM_BIND           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DRM_IOCTL_NOUVEAU_GEM_NEW            DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF        DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI       DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DRM_IOCTL_NOUVEAU_GEM_INFO           DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif /* __NOUVEAU_DRM_H__ */