^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2013 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Author: Rob Clark <robdclark@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The above copyright notice and this permission notice (including the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * paragraph) shall be included in all copies or substantial portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifndef __MSM_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define __MSM_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Please note that modifications to all structs defined here are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * subject to backwards-compatibility constraints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * user/kernel compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * 2) Keep fields aligned to their size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 3) Because of how drm_ioctl() works, we can add new fields at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * the end of an ioctl if some care is taken: drm_ioctl() will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * zero out the new fields at the tail of the ioctl, so a zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * value should have a backwards compatible meaning. And for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * output params, userspace won't see the newly added output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * fields.. so that has to be somehow ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MSM_PIPE_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MSM_PIPE_2D0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MSM_PIPE_2D1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MSM_PIPE_3D0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* The pipe-id just uses the lower bits, so can be OR'd with flags in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * the upper 16 bits (which could be extended further, if needed, maybe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * we extend/overload the pipe-id some day to deal with multiple rings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * but even then I don't think we need the full lower 16 bits).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MSM_PIPE_ID_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* timeouts are specified in clock-monotonic absolute times (to simplify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * restarting interrupted ioctls). The following struct is logically the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * same as 'struct timespec' but 32/64b ABI safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct drm_msm_timespec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __s64 tv_sec; /* seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __s64 tv_nsec; /* nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MSM_PARAM_GPU_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MSM_PARAM_GMEM_SIZE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MSM_PARAM_CHIP_ID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MSM_PARAM_MAX_FREQ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MSM_PARAM_TIMESTAMP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MSM_PARAM_GMEM_BASE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MSM_PARAM_NR_RINGS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MSM_PARAM_FAULTS 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct drm_msm_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __u32 pipe; /* in, MSM_PIPE_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __u32 param; /* in, MSM_PARAM_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __u64 value; /* out (get_param) or in (set_param) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * GEM buffers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MSM_BO_GPU_READONLY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MSM_BO_CACHE_MASK 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* cache modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MSM_BO_CACHED 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MSM_BO_WC 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MSM_BO_UNCACHED 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MSM_BO_GPU_READONLY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MSM_BO_CACHED | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MSM_BO_WC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MSM_BO_UNCACHED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct drm_msm_gem_new {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __u64 size; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __u32 flags; /* in, mask of MSM_BO_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __u32 handle; /* out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Get or set GEM buffer info. The requested value can be passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * directly in 'value', or for data larger than 64b 'value' is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * pointer to userspace buffer, with 'len' specifying the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * bytes copied into that buffer. For info returned by pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * calling the GEM_INFO ioctl with null 'value' will return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * required buffer size in 'len'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct drm_msm_gem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __u32 handle; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __u32 info; /* in - one of MSM_INFO_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __u64 value; /* in or out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __u32 len; /* in or out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MSM_PREP_READ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MSM_PREP_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MSM_PREP_NOSYNC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct drm_msm_gem_cpu_prep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __u32 handle; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __u32 op; /* in, mask of MSM_PREP_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct drm_msm_timespec timeout; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct drm_msm_gem_cpu_fini {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __u32 handle; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Cmdstream Submission:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* The value written into the cmdstream is logically:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * ((relocbuf->gpuaddr + reloc_offset) << shift) | or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * When we have GPU's w/ >32bit ptrs, it should be possible to deal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * with this by emit'ing two reloc entries with appropriate shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * NOTE that reloc's must be sorted by order of increasing submit_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * otherwise EINVAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct drm_msm_gem_submit_reloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __u32 submit_offset; /* in, offset from submit_bo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __u32 or; /* in, value OR'd with result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) __s32 shift; /* in, amount of left shift (can be negative) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __u32 reloc_idx; /* in, index of reloc_bo buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) __u64 reloc_offset; /* in, offset from start of reloc_bo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* submit-types:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * BUF - this cmd buffer is executed normally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * processed normally, but the kernel does not setup an IB to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * this buffer in the first-level ringbuffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * CTX_RESTORE_BUF - only executed if there has been a GPU context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * switch since the last SUBMIT ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MSM_SUBMIT_CMD_BUF 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct drm_msm_gem_submit_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __u32 type; /* in, one of MSM_SUBMIT_CMD_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __u32 submit_offset; /* in, offset into submit_bo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __u32 size; /* in, cmdstream size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __u32 nr_relocs; /* in, number of submit_reloc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __u64 relocs; /* in, ptr to array of submit_reloc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * cmdstream buffer(s) themselves or reloc entries) has one (and only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * one) entry in the submit->bos[] table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * As a optimization, the current buffer (gpu virtual address) can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * passed back through the 'presumed' field. If on a subsequent reloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * userspace passes back a 'presumed' address that is still valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * then patching the cmdstream for this entry is skipped. This can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * avoid kernel needing to map/access the cmdstream bo in the common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MSM_SUBMIT_BO_READ 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MSM_SUBMIT_BO_WRITE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MSM_SUBMIT_BO_DUMP 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MSM_SUBMIT_BO_WRITE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MSM_SUBMIT_BO_DUMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct drm_msm_gem_submit_bo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __u32 handle; /* in, GEM handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __u64 presumed; /* in/out, presumed buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Valid submit ioctl flags: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MSM_SUBMIT_FLAGS ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MSM_SUBMIT_NO_IMPLICIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MSM_SUBMIT_FENCE_FD_IN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MSM_SUBMIT_FENCE_FD_OUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MSM_SUBMIT_SUDO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MSM_SUBMIT_SYNCOBJ_IN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MSM_SUBMIT_SYNCOBJ_OUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MSM_SUBMIT_SYNCOBJ_FLAGS ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MSM_SUBMIT_SYNCOBJ_RESET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct drm_msm_gem_submit_syncobj {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __u32 handle; /* in, syncobj handle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __u64 point; /* in, timepoint for timeline syncobjs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Each cmdstream submit consists of a table of buffers involved, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * one or more cmdstream buffers. This allows for conditional execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * (context-restore), and IB buffers needed for per tile/bin draw cmds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct drm_msm_gem_submit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __u32 fence; /* out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) __u32 nr_bos; /* in, number of submit_bo's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __u32 nr_cmds; /* in, number of submit_cmd's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __u64 bos; /* in, ptr to array of submit_bo's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __u64 cmds; /* in, ptr to array of submit_cmd's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __u32 queueid; /* in, submitqueue id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) __u64 in_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __u64 out_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __u32 syncobj_stride; /* in, stride of syncobj arrays. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __u32 pad; /*in, reserved for future use, always 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* The normal way to synchronize with the GPU is just to CPU_PREP on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * a buffer if you need to access it from the CPU (other cmdstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * handle the required synchronization under the hood). This ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * mainly just exists as a way to implement the gallium pipe_fence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * APIs without requiring a dummy bo to synchronize on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct drm_msm_wait_fence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __u32 fence; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct drm_msm_timespec timeout; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) __u32 queueid; /* in, submitqueue id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* madvise provides a way to tell the kernel in case a buffers contents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * can be discarded under memory pressure, which is useful for userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * bo cache where we want to optimistically hold on to buffer allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * and potential mmap, but allow the pages to be discarded under memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * pressure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Typical usage would involve madvise(DONTNEED) when buffer enters BO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * In the WILLNEED case, 'retained' indicates to userspace whether the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * backing pages still exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MSM_MADV_DONTNEED 1 /* backing pages not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define __MSM_MADV_PURGED 2 /* internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct drm_msm_gem_madvise {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __u32 handle; /* in, GEM handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __u32 madv; /* in, MSM_MADV_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __u32 retained; /* out, whether backing store still exists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Draw queues allow the user to set specific submission parameter. Command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * submissions specify a specific submitqueue to use. ID 0 is reserved for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * backwards compatibility as a "default" submitqueue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MSM_SUBMITQUEUE_FLAGS (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct drm_msm_submitqueue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __u32 flags; /* in, MSM_SUBMITQUEUE_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) __u32 prio; /* in, Priority level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) __u32 id; /* out, identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MSM_SUBMITQUEUE_PARAM_FAULTS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct drm_msm_submitqueue_query {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __u64 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __u32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) __u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DRM_MSM_GET_PARAM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* placeholder:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DRM_MSM_SET_PARAM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DRM_MSM_GEM_NEW 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DRM_MSM_GEM_INFO 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DRM_MSM_GEM_CPU_PREP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DRM_MSM_GEM_CPU_FINI 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DRM_MSM_GEM_SUBMIT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DRM_MSM_WAIT_FENCE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DRM_MSM_GEM_MADVISE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* placeholder:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DRM_MSM_GEM_SVM_NEW 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DRM_MSM_SUBMITQUEUE_NEW 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif /* __MSM_DRM_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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