^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The above copyright notice and this permission notice (including the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * paragraph) shall be included in all copies or substantial portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Jeff Hartmann <jhartmann@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Keith Whitwell <keith@tungstengraphics.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Rewritten by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Gareth Hughes <gareth@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifndef __MGA_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define __MGA_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* WARNING: If you change any of these defines, make sure to change the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * defines in the Xserver file (mga_sarea.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #ifndef __MGA_SAREA_DEFINES__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define __MGA_SAREA_DEFINES__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* WARP pipe flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MGA_F 0x1 /* fog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MGA_A 0x2 /* alpha */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MGA_S 0x4 /* specular */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MGA_T2 0x8 /* multitexture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MGA_WARP_TGZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MGA_WARP_TGZF (MGA_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MGA_WARP_TGZA (MGA_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MGA_WARP_TGZAF (MGA_F|MGA_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MGA_WARP_TGZS (MGA_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MGA_WARP_TGZSF (MGA_S|MGA_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MGA_WARP_TGZSA (MGA_S|MGA_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MGA_WARP_T2GZ (MGA_T2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MGA_WARP_T2GZF (MGA_T2|MGA_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MGA_WARP_T2GZA (MGA_T2|MGA_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MGA_WARP_T2GZS (MGA_T2|MGA_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MGA_MAX_G200_PIPES 8 /* no multitex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MGA_MAX_G400_PIPES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MGA_CARD_TYPE_G200 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MGA_CARD_TYPE_G400 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MGA_CARD_TYPE_G450 3 /* not currently used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MGA_CARD_TYPE_G550 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MGA_FRONT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MGA_BACK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MGA_DEPTH 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* What needs to be changed for the current vertex dma buffer?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MGA_UPLOAD_CONTEXT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MGA_UPLOAD_TEX0 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MGA_UPLOAD_TEX1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MGA_UPLOAD_PIPE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MGA_UPLOAD_2D 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MGA_WAIT_AGE 0x80 /* handled client-side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) quiescent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* 32 buffers of 64k each, total 2 meg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MGA_BUFFER_SIZE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MGA_NUM_BUFFERS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Keep these small for testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MGA_NR_SAREA_CLIPRECTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* 2 heaps (1 for card, 1 for agp), each divided into up to 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * regions, subject to a minimum region size of (1<<16) == 64k.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Clients may subdivide regions internally, but when sharing between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * clients, the region size is the minimum granularity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MGA_CARD_HEAP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MGA_AGP_HEAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MGA_NR_TEX_HEAPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MGA_NR_TEX_REGIONS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MGA_LOG_MIN_TEX_REGION_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DRM_MGA_IDLE_RETRY 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif /* __MGA_SAREA_DEFINES__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Setup registers for 3D context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int dstorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int maccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int plnwt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int dwgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int alphactrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int fogcolor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int wflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int tdualstage0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int tdualstage1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int fcol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int stencil;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int stencilctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } drm_mga_context_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Setup registers for 2D, X server
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } drm_mga_server_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Setup registers for each texture unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int texctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int texctl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int texfilter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int texbordercol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int texorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int texwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int texheight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int texorg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int texorg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int texorg3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int texorg4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } drm_mga_texture_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* General aging mechanism
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int head; /* Position of head pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned int wrap; /* Primary DMA wrap count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } drm_mga_age_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) typedef struct _drm_mga_sarea {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* The channel for communication of state information to the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * on firing a vertex dma buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) drm_mga_context_regs_t context_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) drm_mga_server_regs_t server_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) drm_mga_texture_regs_t tex_state[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int warp_pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int vertsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* The current cliprects, or a subset thereof.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int nbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Information about the most recently used 3d drawable. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * client fills in the req_* fields, the server fills in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * exported_ fields and puts the cliprects into boxes, above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * The client clears the exported_drawable field before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * clobbering the boxes data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int req_drawable; /* the X drawable id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int exported_drawable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int exported_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int exported_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int exported_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int exported_nfront;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int exported_nback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int exported_back_x, exported_front_x, exported_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int exported_back_y, exported_front_y, exported_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Counters for aging textures and for client-side throttling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int status[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int last_wrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) drm_mga_age_t last_frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int last_enqueue; /* last time a buffer was enqueued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int last_dispatch; /* age of the most recently dispatched buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int last_quiescent; /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* LRU lists for texture memory in agp space and on the card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int texAge[MGA_NR_TEX_HEAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Mechanism to validate card state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ctxOwner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } drm_mga_sarea_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* MGA specific ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * The device specific ioctl range is 0x40 to 0x79.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DRM_MGA_INIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DRM_MGA_FLUSH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DRM_MGA_RESET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DRM_MGA_SWAP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DRM_MGA_CLEAR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DRM_MGA_VERTEX 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DRM_MGA_INDICES 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DRM_MGA_ILOAD 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DRM_MGA_BLIT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DRM_MGA_GETPARAM 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* 3.2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * ioctls for operating on fences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DRM_MGA_SET_FENCE 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DRM_MGA_WAIT_FENCE 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DRM_MGA_DMA_BOOTSTRAP 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) typedef struct _drm_mga_warp_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int installed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } drm_mga_warp_index_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) typedef struct drm_mga_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MGA_INIT_DMA = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MGA_CLEANUP_DMA = 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long sarea_priv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int sgram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int maccess;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int fb_cpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned int front_offset, front_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int back_offset, back_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int depth_cpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int depth_offset, depth_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int texture_offset[MGA_NR_TEX_HEAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int texture_size[MGA_NR_TEX_HEAPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned long fb_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long mmio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned long status_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long warp_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned long primary_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long buffers_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } drm_mga_init_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) typedef struct drm_mga_dma_bootstrap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * \name AGP texture region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * be filled in with the actual AGP texture settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * \warning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * is zero, it means that PCI memory (most likely through the use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * an IOMMU) is being used for "AGP" textures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*@{ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned long texture_handle; /**< Handle used to map AGP textures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) __u32 texture_size; /**< Size of the AGP texture region. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*@} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Requested size of the primary DMA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * filled in with the actual AGP mode. If AGP was not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) __u32 primary_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Requested number of secondary DMA buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * filled in with the actual number of secondary DMA buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * allocated. Particularly when PCI DMA is used, this may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * (subtantially) less than the number requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __u32 secondary_bin_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Requested size of each secondary DMA buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * While the kernel \b is free to reduce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __u32 secondary_bin_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * zero, it means that PCI DMA should be used, even if AGP is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * filled in with the actual AGP mode. If AGP was not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * (i.e., PCI DMA was used), this value will be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) __u32 agp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Desired AGP GART size, measured in megabytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __u8 agp_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } drm_mga_dma_bootstrap_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) typedef struct drm_mga_clear {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int clear_color;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned int clear_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int color_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int depth_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } drm_mga_clear_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) typedef struct drm_mga_vertex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int idx; /* buffer to queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int used; /* bytes in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int discard; /* client finished with buffer? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) } drm_mga_vertex_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) typedef struct drm_mga_indices {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int idx; /* buffer to queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int discard; /* client finished with buffer? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } drm_mga_indices_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) typedef struct drm_mga_iload {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int dstorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) } drm_mga_iload_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) typedef struct _drm_mga_blit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned int planemask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int srcorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int dstorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int src_pitch, dst_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int delta_sx, delta_sy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int delta_dx, delta_dy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int height, ydir; /* flip image vertically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int source_pitch, dest_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) } drm_mga_blit_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* 3.1: An ioctl to get parameters that aren't available to the 3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * client any other way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MGA_PARAM_IRQ_NR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* 3.2: Query the actual card type. The DDX only distinguishes between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * G200 chips and non-G200 chips, which it calls G400. It turns out that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * there are some very sublte differences between the G4x0 chips and the G550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * chips. Using this parameter query, a client-side driver can detect the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * difference between a G4x0 and a G550.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MGA_PARAM_CARD_TYPE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) typedef struct drm_mga_getparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void __user *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } drm_mga_getparam_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags