^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef __LIMA_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define __LIMA_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) enum drm_lima_param_gpu_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) DRM_LIMA_PARAM_GPU_ID_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) DRM_LIMA_PARAM_GPU_ID_MALI400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) DRM_LIMA_PARAM_GPU_ID_MALI450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum drm_lima_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DRM_LIMA_PARAM_GPU_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DRM_LIMA_PARAM_NUM_PP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DRM_LIMA_PARAM_GP_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DRM_LIMA_PARAM_PP_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * get various information of the GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct drm_lima_get_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __u32 param; /* in, value in enum drm_lima_param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) __u32 pad; /* pad, must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __u64 value; /* out, parameter value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * heap buffer dynamically increase backup memory size when GP task fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * due to lack of heap memory. size field of heap buffer is an up bound of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * the backup memory which can be set to a fairly large value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LIMA_BO_FLAG_HEAP (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * create a buffer for used by GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct drm_lima_gem_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __u32 size; /* in, buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __u32 flags; /* in, buffer flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __u32 handle; /* out, GEM buffer handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __u32 pad; /* pad, must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * get information of a buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct drm_lima_gem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) __u32 handle; /* in, GEM buffer handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __u32 va; /* out, virtual address mapped into GPU MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __u64 offset; /* out, used to mmap this buffer to CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LIMA_SUBMIT_BO_READ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LIMA_SUBMIT_BO_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* buffer information used by one task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct drm_lima_gem_submit_bo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __u32 handle; /* in, GEM buffer handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __u32 flags; /* in, buffer read/write by GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LIMA_GP_FRAME_REG_NUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* frame used to setup GP for each task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct drm_lima_gp_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __u32 frame[LIMA_GP_FRAME_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LIMA_PP_FRAME_REG_NUM 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LIMA_PP_WB_REG_NUM 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* frame used to setup mali400 GPU PP for each task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct drm_lima_m400_pp_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __u32 frame[LIMA_PP_FRAME_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __u32 num_pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __u32 wb[3 * LIMA_PP_WB_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __u32 plbu_array_address[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __u32 fragment_stack_address[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* frame used to setup mali450 GPU PP for each task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct drm_lima_m450_pp_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __u32 frame[LIMA_PP_FRAME_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __u32 num_pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __u32 wb[3 * LIMA_PP_WB_REG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __u32 use_dlbu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __u32 plbu_array_address[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __u32 dlbu_regs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __u32 fragment_stack_address[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LIMA_PIPE_GP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LIMA_PIPE_PP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * submit a task to GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * User can always merge multi sync_file and drm_syncobj
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * into one drm_syncobj as in_sync[0], but we reserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * in_sync[1] for another task's out_sync to avoid the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * export/import/merge pass when explicit sync.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct drm_lima_gem_submit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __u32 ctx; /* in, context handle task is submitted to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __u32 pipe; /* in, which pipe to use, GP/PP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __u32 nr_bos; /* in, array length of bos field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __u32 frame_size; /* in, size of frame field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __u64 bos; /* in, array of drm_lima_gem_submit_bo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __u64 frame; /* in, GP/PP frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __u32 flags; /* in, submit flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __u32 out_sync; /* in, drm_syncobj handle used to wait task finish after submission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LIMA_GEM_WAIT_READ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LIMA_GEM_WAIT_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * wait pending GPU task finish of a buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct drm_lima_gem_wait {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __u32 handle; /* in, GEM buffer handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __u32 op; /* in, CPU want to read/write this buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __s64 timeout_ns; /* in, wait timeout in absulute time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * create a context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct drm_lima_ctx_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __u32 id; /* out, context handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __u32 _pad; /* pad, must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * free a context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct drm_lima_ctx_free {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __u32 id; /* in, context handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __u32 _pad; /* pad, must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DRM_LIMA_GET_PARAM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DRM_LIMA_GEM_CREATE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DRM_LIMA_GEM_INFO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DRM_LIMA_GEM_SUBMIT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DRM_LIMA_GEM_WAIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DRM_LIMA_CTX_CREATE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DRM_LIMA_CTX_FREE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif /* __LIMA_DRM_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags