^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * copy of this software and associated documentation files (the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * "Software"), to deal in the Software without restriction, including
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * without limitation the rights to use, copy, modify, merge, publish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * distribute, sub license, and/or sell copies of the Software, and to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * permit persons to whom the Software is furnished to do so, subject to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The above copyright notice and this permission notice (including the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * next paragraph) shall be included in all copies or substantial portions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifndef _UAPI_I915_DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define _UAPI_I915_DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Please note that modifications to all structs defined here are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * subject to backwards-compatibility constraints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * DOC: uevents generated by i915 on it's device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * event from the gpu l3 cache. Additional information supplied is ROW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * track of these events and if a specific cache-line seems to have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * persistent error remap it with the l3 remapping tool supplied in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * intel-gpu-tools. The value supplied with the event is always 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * I915_ERROR_UEVENT - Generated upon error detection, currently only via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * hangcheck. The error detection event is a good indicator of when things
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * began to go badly. The value supplied with the event is a 1 upon error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * detection, and a 0 upon reset completion, signifying no more error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * exists. NOTE: Disabling hangcheck or reset via module parameter will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * cause the related events to not be seen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * GPU. The value supplied with the event is always 1. NOTE: Disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * reset via module parameter will cause this event to not be seen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I915_ERROR_UEVENT "ERROR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I915_RESET_UEVENT "RESET"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * i915_user_extension: Base class for defining a chain of extensions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Many interfaces need to grow over time. In most cases we can simply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * extend the struct and have userspace pass in more data. Another option,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * as demonstrated by Vulkan's approach to providing extensions for forward
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * and backward compatibility, is to use a list of optional structs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * provide those extra details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * The key advantage to using an extension chain is that it allows us to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * redefine the interface more easily than an ever growing struct of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * increasing complexity, and for large parts of that interface to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * entirely optional. The downside is more pointer chasing; chasing across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * the __user boundary with pointers encapsulated inside u64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i915_user_extension {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __u64 next_extension;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __u32 name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __u32 flags; /* All undefined bits must be zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __u32 rsvd[4]; /* Reserved for future use; must be zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * MOCS indexes used for GPU surfaces, defining the cacheability of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum i915_mocs_table_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Not cached anywhere, coherency between CPU and GPU accesses is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * guaranteed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) I915_MOCS_UNCACHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Cacheability and coherency controlled by the kernel automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * usage of the surface (used for display scanout or not).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) I915_MOCS_PTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Cached in all GPU caches available on the platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Coherency between CPU and GPU accesses to the surface is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * guaranteed without extra synchronization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) I915_MOCS_CACHED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Different engines serve different roles, and there may be more than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * engine serving each role. enum drm_i915_gem_engine_class provides a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * classification of the role of the engine, which may be used when requesting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * operations to be performed on a certain subset of engines, or for providing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * information about that group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enum drm_i915_gem_engine_class {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) I915_ENGINE_CLASS_RENDER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) I915_ENGINE_CLASS_COPY = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) I915_ENGINE_CLASS_VIDEO = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* should be kept compact */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) I915_ENGINE_CLASS_INVALID = -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * There may be more than one engine fulfilling any role within the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Each engine of a class is given a unique instance number and therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * any engine can be specified by its class:instance tuplet. APIs that allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * access to any engine in the system will use struct i915_engine_class_instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * for this identification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct i915_engine_class_instance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __u16 engine_class; /* see enum drm_i915_gem_engine_class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __u16 engine_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define I915_ENGINE_CLASS_INVALID_NONE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum drm_i915_pmu_engine_sample {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) I915_SAMPLE_BUSY = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) I915_SAMPLE_WAIT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) I915_SAMPLE_SEMA = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define I915_PMU_SAMPLE_BITS (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define I915_PMU_SAMPLE_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define I915_PMU_CLASS_SHIFT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define __I915_PMU_ENGINE(class, instance, sample) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ((class) << I915_PMU_CLASS_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) (instance) << I915_PMU_SAMPLE_BITS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (sample))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define I915_PMU_ENGINE_BUSY(class, instance) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define I915_PMU_ENGINE_WAIT(class, instance) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define I915_PMU_ENGINE_SEMA(class, instance) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Each region is a minimum of 16k, and there are at most 255 of them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * of chars for next/prev indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define I915_LOG_MIN_TEX_REGION_SIZE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) typedef struct _drm_i915_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) I915_INIT_DMA = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) I915_CLEANUP_DMA = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) I915_RESUME_DMA = 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int mmio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int sarea_priv_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int ring_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int ring_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int front_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int back_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int depth_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int pitch_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int back_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int depth_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int cpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } drm_i915_init_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) typedef struct _drm_i915_sarea {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int last_upload; /* last time texture was uploaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int last_enqueue; /* last time a buffer was enqueued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int last_dispatch; /* age of the most recently dispatched buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ctxOwner; /* last context to upload state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int texAge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int pf_enabled; /* is pageflipping allowed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int pf_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int pf_current_page; /* which buffer is being displayed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int perf_boxes; /* performance boxes to be displayed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int width, height; /* screen size in pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) drm_handle_t front_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int front_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int front_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) drm_handle_t back_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int back_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int back_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) drm_handle_t depth_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int depth_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int depth_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) drm_handle_t tex_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int tex_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int tex_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int log_tex_granularity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int rotation; /* 0, 90, 180 or 270 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int rotated_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int rotated_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int rotated_pitch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int virtualX, virtualY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int front_tiled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int back_tiled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned int depth_tiled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int rotated_tiled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int rotated2_tiled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int pipeA_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int pipeA_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int pipeA_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int pipeA_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int pipeB_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int pipeB_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int pipeB_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int pipeB_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* fill out some space for old userspace triple buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) drm_handle_t unused_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __u32 unused1, unused2, unused3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* buffer object handles for static buffers. May change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * over the lifetime of the client.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __u32 front_bo_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __u32 back_bo_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __u32 unused_bo_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __u32 depth_bo_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } drm_i915_sarea_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* due to userspace building against these headers we need some compat here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define planeA_x pipeA_x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define planeA_y pipeA_y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define planeA_w pipeA_w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define planeA_h pipeA_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define planeB_x pipeB_x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define planeB_y pipeB_y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define planeB_w pipeB_w
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define planeB_h pipeB_h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Flags for perf_boxes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define I915_BOX_RING_EMPTY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define I915_BOX_FLIP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define I915_BOX_WAIT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define I915_BOX_TEXTURE_LOAD 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define I915_BOX_LOST_CONTEXT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * i915 specific ioctls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DRM_I915_INIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DRM_I915_FLUSH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DRM_I915_FLIP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DRM_I915_BATCHBUFFER 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DRM_I915_IRQ_EMIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DRM_I915_IRQ_WAIT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DRM_I915_GETPARAM 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DRM_I915_SETPARAM 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define DRM_I915_ALLOC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DRM_I915_FREE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DRM_I915_INIT_HEAP 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DRM_I915_CMDBUFFER 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DRM_I915_DESTROY_HEAP 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DRM_I915_SET_VBLANK_PIPE 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define DRM_I915_GET_VBLANK_PIPE 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define DRM_I915_VBLANK_SWAP 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define DRM_I915_HWS_ADDR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define DRM_I915_GEM_INIT 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define DRM_I915_GEM_EXECBUFFER 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DRM_I915_GEM_PIN 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DRM_I915_GEM_UNPIN 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DRM_I915_GEM_BUSY 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DRM_I915_GEM_THROTTLE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DRM_I915_GEM_ENTERVT 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DRM_I915_GEM_LEAVEVT 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DRM_I915_GEM_CREATE 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DRM_I915_GEM_PREAD 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DRM_I915_GEM_PWRITE 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DRM_I915_GEM_MMAP 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DRM_I915_GEM_SET_DOMAIN 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DRM_I915_GEM_SW_FINISH 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DRM_I915_GEM_SET_TILING 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DRM_I915_GEM_GET_TILING 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DRM_I915_GEM_GET_APERTURE 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DRM_I915_GEM_MMAP_GTT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DRM_I915_GEM_MADVISE 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DRM_I915_OVERLAY_ATTRS 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DRM_I915_GEM_EXECBUFFER2 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DRM_I915_GEM_WAIT 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DRM_I915_GEM_SET_CACHING 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DRM_I915_GEM_GET_CACHING 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DRM_I915_REG_READ 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DRM_I915_GET_RESET_STATS 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DRM_I915_GEM_USERPTR 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define DRM_I915_PERF_OPEN 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define DRM_I915_PERF_ADD_CONFIG 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define DRM_I915_PERF_REMOVE_CONFIG 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DRM_I915_QUERY 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DRM_I915_GEM_VM_CREATE 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DRM_I915_GEM_VM_DESTROY 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Must be kept compact -- no holes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Allow drivers to submit batchbuffers directly to hardware, relying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * on the security mechanisms provided by hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) typedef struct drm_i915_batchbuffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int start; /* agp offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int used; /* nr bytes in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int num_cliprects; /* mulitpass with multiple cliprects? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } drm_i915_batchbuffer_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* As above, but pass a pointer to userspace buffer which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * validated by the kernel prior to sending to hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) typedef struct _drm_i915_cmdbuffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) char __user *buf; /* pointer to userspace command buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int sz; /* nr bytes in buf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int num_cliprects; /* mulitpass with multiple cliprects? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } drm_i915_cmdbuffer_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Userspace can request & wait on irq's:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) typedef struct drm_i915_irq_emit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int __user *irq_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) } drm_i915_irq_emit_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) typedef struct drm_i915_irq_wait {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int irq_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } drm_i915_irq_wait_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Different modes of per-process Graphics Translation Table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * see I915_PARAM_HAS_ALIASING_PPGTT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define I915_GEM_PPGTT_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define I915_GEM_PPGTT_ALIASING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define I915_GEM_PPGTT_FULL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Ioctl to query kernel params:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define I915_PARAM_IRQ_ACTIVE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define I915_PARAM_ALLOW_BATCHBUFFER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define I915_PARAM_LAST_DISPATCH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define I915_PARAM_CHIPSET_ID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define I915_PARAM_HAS_GEM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define I915_PARAM_NUM_FENCES_AVAIL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define I915_PARAM_HAS_OVERLAY 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define I915_PARAM_HAS_PAGEFLIPPING 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define I915_PARAM_HAS_EXECBUF2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define I915_PARAM_HAS_BSD 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define I915_PARAM_HAS_BLT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define I915_PARAM_HAS_RELAXED_FENCING 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define I915_PARAM_HAS_COHERENT_RINGS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define I915_PARAM_HAS_EXEC_CONSTANTS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define I915_PARAM_HAS_RELAXED_DELTA 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define I915_PARAM_HAS_GEN7_SOL_RESET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define I915_PARAM_HAS_LLC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define I915_PARAM_HAS_ALIASING_PPGTT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define I915_PARAM_HAS_WAIT_TIMEOUT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define I915_PARAM_HAS_SEMAPHORES 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define I915_PARAM_HAS_VEBOX 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define I915_PARAM_HAS_SECURE_BATCHES 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define I915_PARAM_HAS_PINNED_BATCHES 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define I915_PARAM_HAS_EXEC_NO_RELOC 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define I915_PARAM_HAS_WT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define I915_PARAM_CMD_PARSER_VERSION 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define I915_PARAM_MMAP_VERSION 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define I915_PARAM_HAS_BSD2 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define I915_PARAM_REVISION 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define I915_PARAM_SUBSLICE_TOTAL 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define I915_PARAM_EU_TOTAL 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define I915_PARAM_HAS_GPU_RESET 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define I915_PARAM_HAS_RESOURCE_STREAMER 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define I915_PARAM_HAS_EXEC_SOFTPIN 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define I915_PARAM_HAS_POOLED_EU 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define I915_PARAM_MIN_EU_IN_POOL 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define I915_PARAM_MMAP_GTT_VERSION 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * priorities and the driver will attempt to execute batches in priority order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * The param returns a capability bitmask, nonzero implies that the scheduler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * is enabled, with different features present according to the mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * The initial priority for each batch is supplied by the context and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * controlled via I915_CONTEXT_PARAM_PRIORITY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define I915_PARAM_HAS_SCHEDULER 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define I915_PARAM_HUC_STATUS 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * synchronisation with implicit fencing on individual objects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * See EXEC_OBJECT_ASYNC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define I915_PARAM_HAS_EXEC_ASYNC 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * both being able to pass in a sync_file fd to wait upon before executing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * and being able to return a new sync_file fd that is signaled when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define I915_PARAM_HAS_EXEC_FENCE 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * user specified bufffers for post-mortem debugging of GPU hangs. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * EXEC_OBJECT_CAPTURE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define I915_PARAM_HAS_EXEC_CAPTURE 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define I915_PARAM_SLICE_MASK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Assuming it's uniform for each slice, this queries the mask of subslices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * per-slice for this system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define I915_PARAM_SUBSLICE_MASK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * Query whether every context (both per-file default and user created) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * isolated (insofar as HW supports). If this parameter is not true, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * freshly created contexts may inherit values from an existing context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * rather than default HW values. If true, it also ensures (insofar as HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * supports) that all state set by this context will not leak to any other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * As not every engine across every gen support contexts, the returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * value reports the support of context isolation for individual engines by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * returning a bitmask of each engine class set to true if that class supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * isolation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define I915_PARAM_HAS_CONTEXT_ISOLATION 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Frequency of the command streamer timestamps given by the *_TIMESTAMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * registers. This used to be fixed per platform but from CNL onwards, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * might vary depending on the parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * Once upon a time we supposed that writes through the GGTT would be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * immediately in physical memory (once flushed out of the CPU path). However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * on a few different processors and chipsets, this is not necessarily the case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * as the writes appear to be buffered internally. Thus a read of the backing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * storage (physical memory) via a different path (with different physical tags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * to the indirect write via the GGTT) will see stale values from before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * the GGTT write. Inside the kernel, we can for the most part keep track of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * the different read/write domains in use (e.g. set-domain), but the assumption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * of coherency is baked into the ABI, hence reporting its true state in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * Reports true when writes via mmap_gtt are immediately visible following an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * lfence to flush the WCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * Reports false when writes via mmap_gtt are indeterminately delayed in an in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * internal buffer and are _not_ immediately visible to third parties accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * communications channel when reporting false is strongly disadvised.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define I915_PARAM_MMAP_GTT_COHERENT 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * execution through use of explicit fence support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * Revision of the i915-perf uAPI. The value returned helps determine what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * i915-perf features are available. See drm_i915_perf_property_id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define I915_PARAM_PERF_REVISION 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * I915_EXEC_USE_EXTENSIONS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Must be kept compact -- no holes and well documented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) typedef struct drm_i915_getparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) __s32 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * WARNING: Using pointers instead of fixed-size u64 means we need to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * compat32 code. Don't repeat this mistake.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int __user *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) } drm_i915_getparam_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Ioctl to set kernel params:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define I915_SETPARAM_NUM_USED_FENCES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Must be kept compact -- no holes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) typedef struct drm_i915_setparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) } drm_i915_setparam_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* A memory manager for regions of shared memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define I915_MEM_REGION_AGP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) typedef struct drm_i915_mem_alloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int __user *region_offset; /* offset from start of fb or agp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) } drm_i915_mem_alloc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) typedef struct drm_i915_mem_free {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int region_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) } drm_i915_mem_free_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) typedef struct drm_i915_mem_init_heap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) } drm_i915_mem_init_heap_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Allow memory manager to be torn down and re-initialized (eg on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * rotate):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) typedef struct drm_i915_mem_destroy_heap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) } drm_i915_mem_destroy_heap_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Allow X server to configure which pipes to monitor for vblank signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define DRM_I915_VBLANK_PIPE_A 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define DRM_I915_VBLANK_PIPE_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) typedef struct drm_i915_vblank_pipe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } drm_i915_vblank_pipe_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Schedule buffer swap at given vertical blank:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) typedef struct drm_i915_vblank_swap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) drm_drawable_t drawable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) enum drm_vblank_seq_type seqtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned int sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) } drm_i915_vblank_swap_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) typedef struct drm_i915_hws_addr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) __u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) } drm_i915_hws_addr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct drm_i915_gem_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * Beginning offset in the GTT to be managed by the DRM memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) __u64 gtt_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * Ending offset in the GTT to be managed by the DRM memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __u64 gtt_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct drm_i915_gem_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * Requested size for the object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * The (page-aligned) allocated size for the object will be returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * Returned handle for the object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * Object handles are nonzero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct drm_i915_gem_pread {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /** Handle for the object being read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /** Offset into the object to read from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /** Length of data to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * Pointer to write the data into.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * This is a fixed-size type for 32/64 compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) __u64 data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct drm_i915_gem_pwrite {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /** Handle for the object being written to. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /** Offset into the object to write to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /** Length of data to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * Pointer to read the data from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * This is a fixed-size type for 32/64 compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) __u64 data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct drm_i915_gem_mmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /** Handle for the object being mapped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /** Offset in the object to map. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * Length of data to map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * The value will be page-aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * Returned pointer the data was mapped at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * This is a fixed-size type for 32/64 compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) __u64 addr_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Flags for extended behaviour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * Added in version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) __u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define I915_MMAP_WC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct drm_i915_gem_mmap_gtt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /** Handle for the object being mapped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * Fake offset to use for subsequent mmap call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * This is a fixed-size type for 32/64 compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct drm_i915_gem_mmap_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /** Handle for the object being mapped. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * Fake offset to use for subsequent mmap call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * This is a fixed-size type for 32/64 compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * Flags for extended behaviour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * It is mandatory that one of the MMAP_OFFSET types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * (GTT, WC, WB, UC, etc) should be included.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) __u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define I915_MMAP_OFFSET_GTT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define I915_MMAP_OFFSET_WC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define I915_MMAP_OFFSET_WB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define I915_MMAP_OFFSET_UC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * Zero-terminated chain of extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * No current extensions defined; mbz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) __u64 extensions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct drm_i915_gem_set_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /** Handle for the object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /** New read domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) __u32 read_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /** New write domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) __u32 write_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct drm_i915_gem_sw_finish {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /** Handle for the object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct drm_i915_gem_relocation_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Handle of the buffer being pointed to by this relocation entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * It's appealing to make this be an index into the mm_validate_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * list to refer to the buffer, but this allows the driver to create
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * a relocation list for state buffers and not re-write it per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * exec using the buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) __u32 target_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * Value to be added to the offset of the target buffer to make up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * the relocation entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) __u32 delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /** Offset in the buffer the relocation entry will be written into */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * Offset value of the target buffer that the relocation entry was last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * written as.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * If the buffer has the same offset as last time, we can skip syncing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * and writing the relocation. This value is written back out by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * the execbuffer ioctl when the relocation is written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) __u64 presumed_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * Target memory domains read by this operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) __u32 read_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * Target memory domains written by this operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * Note that only one domain may be written by the whole
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * execbuffer operation, so that where there are conflicts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * the application will get -EINVAL back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) __u32 write_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /** @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * Intel memory domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * Most of these just align with the various caches in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * the system and are used to flush and invalidate as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * objects end up cached in different domains.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /** CPU cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define I915_GEM_DOMAIN_CPU 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /** Render cache, used by 2D and 3D drawing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define I915_GEM_DOMAIN_RENDER 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /** Sampler cache, used by texture engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define I915_GEM_DOMAIN_SAMPLER 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /** Command queue, used to load batch buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define I915_GEM_DOMAIN_COMMAND 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /** Instruction cache, used by shader programs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /** Vertex address cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define I915_GEM_DOMAIN_VERTEX 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /** GTT domain - aperture and scanout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define I915_GEM_DOMAIN_GTT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /** WC domain - uncached access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define I915_GEM_DOMAIN_WC 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /** @} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct drm_i915_gem_exec_object {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * User's handle for a buffer to be bound into the GTT for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /** Number of relocations to be performed on this buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) __u32 relocation_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * Pointer to array of struct drm_i915_gem_relocation_entry containing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * the relocations to be performed in this buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) __u64 relocs_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /** Required alignment in graphics aperture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) __u64 alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * Returned value of the updated offset of the object, for future
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * presumed_offset writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct drm_i915_gem_execbuffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * List of buffers to be validated with their relocations to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * performend on them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * This is a pointer to an array of struct drm_i915_gem_validate_entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * These buffers must be listed in an order such that all relocations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * a buffer is performing refer to buffers that have already appeared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * in the validate list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) __u64 buffers_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) __u32 buffer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /** Offset in the batchbuffer to start execution from. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) __u32 batch_start_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /** Bytes used in batchbuffer from batch_start_offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) __u32 batch_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) __u32 DR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) __u32 DR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) __u32 num_cliprects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /** This is a struct drm_clip_rect *cliprects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) __u64 cliprects_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct drm_i915_gem_exec_object2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * User's handle for a buffer to be bound into the GTT for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /** Number of relocations to be performed on this buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) __u32 relocation_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * Pointer to array of struct drm_i915_gem_relocation_entry containing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * the relocations to be performed in this buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) __u64 relocs_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /** Required alignment in graphics aperture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) __u64 alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * When the EXEC_OBJECT_PINNED flag is specified this is populated by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * the user with the GTT offset at which this object will be pinned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * When the I915_EXEC_NO_RELOC flag is specified this must contain the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * presumed_offset of the object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * During execbuffer2 the kernel populates it with the value of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * current GTT offset of the object, for future presumed_offset writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define EXEC_OBJECT_NEEDS_GTT (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define EXEC_OBJECT_WRITE (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define EXEC_OBJECT_PINNED (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* The kernel implicitly tracks GPU activity on all GEM objects, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * synchronises operations with outstanding rendering. This includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * rendering on other devices if exported via dma-buf. However, sometimes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * this tracking is too coarse and the user knows better. For example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * if the object is split into non-overlapping ranges shared between different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * clients or engines (i.e. suballocating objects), the implicit tracking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * by kernel assumes that each operation affects the whole object rather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * than an individual range, causing needless synchronisation between clients.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * The kernel will also forgo any CPU cache flushes prior to rendering from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * the object as the client is expected to be also handling such domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * tracking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * The kernel maintains the implicit tracking in order to manage resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * used by the GPU - this flag only disables the synchronisation prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * rendering with this object in this execbuf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * Opting out of implicit synhronisation requires the user to do its own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * explicit tracking to avoid rendering corruption. See, for example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define EXEC_OBJECT_ASYNC (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* Request that the contents of this execobject be copied into the error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * state upon a GPU hang involving this batch for post-mortem debugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * These buffers are recorded in no particular order as "user" in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * if the kernel supports this flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define EXEC_OBJECT_CAPTURE (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) __u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) __u64 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) __u64 pad_to_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) __u64 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct drm_i915_gem_exec_fence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * User's handle for a drm_syncobj to wait on or signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define I915_EXEC_FENCE_WAIT (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define I915_EXEC_FENCE_SIGNAL (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * See drm_i915_gem_execbuffer_ext_timeline_fences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * This structure describes an array of drm_syncobj and associated points for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * timeline variants of drm_syncobj. It is invalid to append this structure to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * the execbuf if I915_EXEC_FENCE_ARRAY is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct drm_i915_gem_execbuffer_ext_timeline_fences {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct i915_user_extension base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * Number of element in the handles_ptr & value_ptr arrays.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) __u64 fence_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * Pointer to an array of struct drm_i915_gem_exec_fence of length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * fence_count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) __u64 handles_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * Pointer to an array of u64 values of length fence_count. Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) __u64 values_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct drm_i915_gem_execbuffer2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * List of gem_exec_object2 structs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) __u64 buffers_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) __u32 buffer_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /** Offset in the batchbuffer to start execution from. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) __u32 batch_start_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /** Bytes used in batchbuffer from batch_start_offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) __u32 batch_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) __u32 DR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) __u32 DR4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) __u32 num_cliprects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) * This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * & I915_EXEC_USE_EXTENSIONS are not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * of struct drm_i915_gem_exec_fence and num_cliprects is the length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * of the array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * single struct i915_user_extension and num_cliprects is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) __u64 cliprects_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define I915_EXEC_RING_MASK (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define I915_EXEC_DEFAULT (0<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define I915_EXEC_RENDER (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define I915_EXEC_BSD (2<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define I915_EXEC_BLT (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define I915_EXEC_VEBOX (4<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Used for switching the constants addressing mode on gen4+ RENDER ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * Gen6+ only supports relative addressing to dynamic state (default) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * absolute addressing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * These flags are ignored for the BSD and BLT rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define I915_EXEC_CONSTANTS_MASK (3<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) __u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) __u64 rsvd1; /* now used for context info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) __u64 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /** Resets the SO write offset registers for transform feedback on gen7. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define I915_EXEC_GEN7_SOL_RESET (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /** Request a privileged ("secure") batch buffer. Note only available for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * DRM_ROOT_ONLY | DRM_MASTER processes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define I915_EXEC_SECURE (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /** Inform the kernel that the batch is and will always be pinned. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * negates the requirement for a workaround to be performed to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * an incoherent CS (such as can be found on 830/845). If this flag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * not passed, the kernel will endeavour to make sure the batch is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * coherent with the CS before execution. If this flag is passed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * userspace assumes the responsibility for ensuring the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define I915_EXEC_IS_PINNED (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /** Provide a hint to the kernel that the command stream and auxiliary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * state buffers already holds the correct presumed addresses and so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * relocation process may be skipped if no buffers need to be moved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * preparation for the execbuffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define I915_EXEC_NO_RELOC (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /** Use the reloc.handle as an index into the exec object array rather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * than as the per-file handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define I915_EXEC_HANDLE_LUT (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /** Used for switching BSD rings on the platforms with two BSD rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define I915_EXEC_BSD_SHIFT (13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* default ping-pong mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /** Tell the kernel that the batchbuffer is processed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * the resource streamer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define I915_EXEC_RESOURCE_STREAMER (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * the batch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * Returns -EINVAL if the sync_file fd cannot be found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define I915_EXEC_FENCE_IN (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * to the caller, and it should be close() after use. (The fd is a regular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * file descriptor and will be cleaned up on process termination. It holds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * a reference to the request, but nothing else.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * The sync_file fd can be combined with other sync_file and passed either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * will only occur after this request completes), or to other devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * Using I915_EXEC_FENCE_OUT requires use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * back to userspace. Failure to do so will cause the out-fence to always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * be reported as zero, and the real fence fd to be leaked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define I915_EXEC_FENCE_OUT (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * Traditionally the execbuf ioctl has only considered the final element in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * the execobject[] to be the executable batch. Often though, the client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * will known the batch object prior to construction and being able to place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * it into the execobject[] array first can simplify the relocation tracking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * execobject[] as the * batch instead (the default is to use the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * element).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define I915_EXEC_BATCH_FIRST (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * define an array of i915_gem_exec_fence structures which specify a set of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * dma fences to wait upon or signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define I915_EXEC_FENCE_ARRAY (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * the batch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * Returns -EINVAL if the sync_file fd cannot be found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define I915_EXEC_FENCE_SUBMIT (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * Setting I915_EXEC_USE_EXTENSIONS implies that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * list of i915_user_extension. Each i915_user_extension node is the base of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * larger structure. The list of supported structures are listed in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * drm_i915_gem_execbuffer_ext enum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define I915_EXEC_USE_EXTENSIONS (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define i915_execbuffer2_set_context_id(eb2, context) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define i915_execbuffer2_get_context_id(eb2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) struct drm_i915_gem_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /** Handle of the buffer to be pinned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /** alignment required within the aperture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) __u64 alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /** Returned GTT offset of the buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct drm_i915_gem_unpin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /** Handle of the buffer to be unpinned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct drm_i915_gem_busy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /** Handle of the buffer to check for busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /** Return busy status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * A return of 0 implies that the object is idle (after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * having flushed any pending activity), and a non-zero return that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * the object is still in-flight on the GPU. (The GPU has not yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * signaled completion for all pending requests that reference the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * object.) An object is guaranteed to become idle eventually (so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * long as no new GPU commands are executed upon it). Due to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * asynchronous nature of the hardware, an object reported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * as busy may become idle before the ioctl is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * Furthermore, if the object is busy, which engine is busy is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) * provided as a guide and only indirectly by reporting its class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * (there may be more than one engine in each class). There are race
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * conditions which prevent the report of which engines are busy from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * being always accurate. However, the converse is not true. If the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * object is idle, the result of the ioctl, that all engines are idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * is accurate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * The returned dword is split into two fields to indicate both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * the engine classess on which the object is being read, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * engine class on which it is currently being written (if any).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * The low word (bits 0:15) indicate if the object is being written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * to by any engine (there can only be one, as the GEM implicit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * synchronisation rules force writes to be serialised). Only the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * 1 not 0 etc) for the last write is reported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * The high word (bits 16:31) are a bitmask of which engines classes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * are currently reading from the object. Multiple engines may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * reading from the object simultaneously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * The value of each engine class is the same as specified in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * reported as active itself. Some hardware may have parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * execution engines, e.g. multiple media engines, which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * mapped to the same class identifier and so are not separately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * reported for busyness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * Caveat emptor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * Only the boolean result of this query is reliable; that is whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * the object is idle or busy. The report of which engines are busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * should be only used as a heuristic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) __u32 busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * I915_CACHING_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * GPU access is not coherent with cpu caches. Default for machines without an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * LLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define I915_CACHING_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * I915_CACHING_CACHED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * GPU access is coherent with cpu caches and furthermore the data is cached in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * last-level caches shared between cpu cores and the gpu GT. Default on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * machines with HAS_LLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define I915_CACHING_CACHED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * I915_CACHING_DISPLAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * Special GPU caching mode which is coherent with the scanout engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * Transparently falls back to I915_CACHING_NONE on platforms where no special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * cache mode (like write-through or gfdt flushing) is available. The kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * automatically sets this mode when using a buffer as a scanout target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * Userspace can manually set this mode to avoid a costly stall and clflush in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * the hotpath of drawing the first frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define I915_CACHING_DISPLAY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) struct drm_i915_gem_caching {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * Handle of the buffer to set/get the caching level of. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * Cacheing level to apply or return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * bits0-15 are for generic caching control (i.e. the above defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) * values). bits16-31 are reserved for platform-specific variations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * (e.g. l3$ caching on gen7). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) __u32 caching;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define I915_TILING_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define I915_TILING_X 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define I915_TILING_Y 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define I915_TILING_LAST I915_TILING_Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define I915_BIT_6_SWIZZLE_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define I915_BIT_6_SWIZZLE_9 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define I915_BIT_6_SWIZZLE_9_10 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define I915_BIT_6_SWIZZLE_9_11 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define I915_BIT_6_SWIZZLE_9_10_11 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* Not seen by userland */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define I915_BIT_6_SWIZZLE_UNKNOWN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* Seen by userland. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define I915_BIT_6_SWIZZLE_9_17 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define I915_BIT_6_SWIZZLE_9_10_17 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) struct drm_i915_gem_set_tiling {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /** Handle of the buffer to have its tiling state updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * I915_TILING_Y).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * This value is to be set on request, and will be updated by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * kernel on successful return with the actual chosen tiling layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * The tiling mode may be demoted to I915_TILING_NONE when the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * has bit 6 swizzling that can't be managed correctly by GEM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * Buffer contents become undefined when changing tiling_mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) __u32 tiling_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * Stride in bytes for the object when in I915_TILING_X or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * I915_TILING_Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) __u32 stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * Returned address bit 6 swizzling required for CPU access through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * mmap mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) __u32 swizzle_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct drm_i915_gem_get_tiling {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /** Handle of the buffer to get tiling state for. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * I915_TILING_Y).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) __u32 tiling_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * Returned address bit 6 swizzling required for CPU access through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * mmap mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) __u32 swizzle_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) * Returned address bit 6 swizzling required for CPU access through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * mmap mapping whilst bound.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) __u32 phys_swizzle_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct drm_i915_gem_get_aperture {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) __u64 aper_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) * Available space in the aperture used by i915_gem_execbuffer, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) __u64 aper_available_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct drm_i915_get_pipe_from_crtc_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /** ID of CRTC being requested **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) __u32 crtc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /** pipe of requested CRTC **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) __u32 pipe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define I915_MADV_WILLNEED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define I915_MADV_DONTNEED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define __I915_MADV_PURGED 2 /* internal state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) struct drm_i915_gem_madvise {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /** Handle of the buffer to change the backing store advice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* Advice: either the buffer will be needed again in the near future,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * or wont be and could be discarded under memory pressure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) __u32 madv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /** Whether the backing store still exists. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) __u32 retained;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define I915_OVERLAY_TYPE_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define I915_OVERLAY_YUV_PLANAR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define I915_OVERLAY_YUV_PACKED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define I915_OVERLAY_RGB 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define I915_OVERLAY_DEPTH_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define I915_OVERLAY_RGB24 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define I915_OVERLAY_RGB16 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define I915_OVERLAY_RGB15 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define I915_OVERLAY_YUV422 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define I915_OVERLAY_YUV411 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define I915_OVERLAY_YUV420 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define I915_OVERLAY_YUV410 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define I915_OVERLAY_SWAP_MASK 0xff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define I915_OVERLAY_NO_SWAP 0x000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define I915_OVERLAY_UV_SWAP 0x010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define I915_OVERLAY_Y_SWAP 0x020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define I915_OVERLAY_FLAGS_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define I915_OVERLAY_ENABLE 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct drm_intel_overlay_put_image {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* various flags and src format description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* source picture description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) __u32 bo_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /* stride values and offsets are in bytes, buffer relative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) __u16 stride_Y; /* stride for packed formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) __u16 stride_UV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) __u32 offset_Y; /* offset for packet formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) __u32 offset_U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) __u32 offset_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* in pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) __u16 src_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) __u16 src_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* to compensate the scaling factors for partially covered surfaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) __u16 src_scan_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) __u16 src_scan_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* output crtc description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) __u32 crtc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) __u16 dst_x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) __u16 dst_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) __u16 dst_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) __u16 dst_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct drm_intel_overlay_attrs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) __u32 color_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) __s32 brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) __u32 contrast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) __u32 saturation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) __u32 gamma0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) __u32 gamma1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) __u32 gamma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) __u32 gamma3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) __u32 gamma4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) __u32 gamma5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * Intel sprite handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * Color keying works with a min/mask/max tuple. Both source and destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * color keying is allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * Source keying:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * Sprite pixels within the min & max values, masked against the color channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) * specified in the mask field, will be transparent. All other pixels will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * be displayed on top of the primary plane. For RGB surfaces, only the min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * and mask fields will be used; ranged compares are not allowed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) * Destination keying:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) * Primary plane pixels that match the min value, masked against the color
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * channels specified in the mask field, will be replaced by corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * pixels from the sprite plane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * Note that source & destination keying are exclusive; only one can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * active on a given plane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * flags==0 to disable colorkeying.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #define I915_SET_COLORKEY_DESTINATION (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define I915_SET_COLORKEY_SOURCE (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) struct drm_intel_sprite_colorkey {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) __u32 plane_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) __u32 min_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) __u32 channel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) __u32 max_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) struct drm_i915_gem_wait {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /** Handle of BO we shall wait on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) __u32 bo_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /** Number of nanoseconds to wait, Returns time remaining. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) __s64 timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) struct drm_i915_gem_context_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) __u32 ctx_id; /* output: id of new context*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) struct drm_i915_gem_context_create_ext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) __u32 ctx_id; /* output: id of new context*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) __u64 extensions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct drm_i915_gem_context_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) __u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) __u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) __u64 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define I915_CONTEXT_PARAM_GTT_SIZE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define I915_CONTEXT_PARAM_BANNABLE 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define I915_CONTEXT_PARAM_PRIORITY 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define I915_CONTEXT_DEFAULT_PRIORITY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) * When using the following param, value should be a pointer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) * drm_i915_gem_context_param_sseu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define I915_CONTEXT_PARAM_SSEU 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) * Not all clients may want to attempt automatic recover of a context after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) * a hang (for example, some clients may only submit very small incremental
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) * batches relying on known logical state of previous batches which will never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) * recover correctly and each attempt will hang), and so would prefer that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) * the context is forever banned instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) * If set to false (0), after a reset, subsequent (and in flight) rendering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) * from this context is discarded, and the client will need to create a new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * context to use instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * If set to true (1), the kernel will automatically attempt to recover the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) * context by skipping the hanging batch and executing the next batch starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * from the default context state (discarding the incomplete logical context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * state lost due to the reset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) * On creation, all new contexts are marked as recoverable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define I915_CONTEXT_PARAM_RECOVERABLE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * The id of the associated virtual memory address space (ppGTT) of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) * this context. Can be retrieved and passed to another context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) * (on the same fd) for both to use the same ppGTT and so share
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) * address layouts, and avoid reloading the page tables on context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) * switches between themselves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define I915_CONTEXT_PARAM_VM 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * I915_CONTEXT_PARAM_ENGINES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * Bind this context to operate on this subset of available engines. Henceforth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * and upwards. Slots 0...N are filled in using the specified (class, instance).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * Use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) * engine_class: I915_ENGINE_CLASS_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * to specify a gap in the array that can be filled in later, e.g. by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * virtual engine used for load balancing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * Setting the number of engines bound to the context to 0, by passing a zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * sized argument, will revert back to default settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * See struct i915_context_param_engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) * Extensions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define I915_CONTEXT_PARAM_ENGINES 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * I915_CONTEXT_PARAM_PERSISTENCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * Allow the context and active rendering to survive the process until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) * completion. Persistence allows fire-and-forget clients to queue up a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) * bunch of work, hand the output over to a display server and then quit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * If the context is marked as not persistent, upon closing (either via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * or process termination), the context and any outstanding requests will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * cancelled (and exported fences for cancelled requests marked as -EIO).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) * By default, new contexts allow persistence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) * I915_CONTEXT_PARAM_RINGSIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) * Sets the size of the CS ringbuffer to use for logical ring contexts. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) * applies a limit of how many batches can be queued to HW before the caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * is blocked due to lack of space for more commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * Only reliably possible to be set prior to first use, i.e. during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) * construction. At any later point, the current execution must be flushed as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) * the ring can only be changed while the context is idle. Note, the ringsize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) * can be specified as a constructor property, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) * I915_CONTEXT_CREATE_EXT_SETPARAM, but can also be set later if required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) * Only applies to the current set of engine and lost when those engines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) * are replaced by a new mapping (see I915_CONTEXT_PARAM_ENGINES).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) * Must be between 4 - 512 KiB, in intervals of page size [4 KiB].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) * Default is 16 KiB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define I915_CONTEXT_PARAM_RINGSIZE 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) /* Must be kept compact -- no holes and well documented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) __u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * Context SSEU programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) * It may be necessary for either functional or performance reason to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) * Sub-slice/EU).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) * This is done by configuring SSEU configuration using the below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) * @struct drm_i915_gem_context_param_sseu for every supported engine which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * userspace intends to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * Not all GPUs or engines support this functionality in which case an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * code -ENODEV will be returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * Also, flexibility of possible SSEU configuration permutations varies between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * GPU generations and software imposed limitations. Requesting such a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * combination will return an error code of -EINVAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * favour of a single global setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct drm_i915_gem_context_param_sseu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) * Engine class & instance to be configured or queried.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) struct i915_engine_class_instance engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) * Unknown flags must be cleared to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * Mask of slices to enable for the context. Valid values are a subset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * of the bitmask value returned for I915_PARAM_SLICE_MASK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) __u64 slice_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) * Mask of subslices to enable for the context. Valid values are a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) __u64 subslice_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * Minimum/Maximum number of EUs to enable per subslice for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * context. min_eus_per_subslice must be inferior or equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * max_eus_per_subslice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) __u16 min_eus_per_subslice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) __u16 max_eus_per_subslice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * Unused for now. Must be cleared to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) __u32 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) * i915_context_engines_load_balance:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) * Enable load balancing across this set of engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * used will proxy the execbuffer request onto one of the set of engines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * in such a way as to distribute the load evenly across the set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) * The set of engines must be compatible (e.g. the same HW class) as they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) * will share the same logical GPU context and ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * To intermix rendering with the virtual engine and direct rendering onto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * the backing engines (bypassing the load balancing proxy), the context must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * be defined to use a single timeline for all engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct i915_context_engines_load_balance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) struct i915_user_extension base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) __u16 engine_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) __u16 num_siblings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) __u32 flags; /* all undefined flags must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) __u64 mbz64; /* reserved for future use; must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) struct i915_engine_class_instance engines[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) struct i915_user_extension base; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) __u16 engine_index; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) __u16 num_siblings; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) __u32 flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) __u64 mbz64; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct i915_engine_class_instance engines[N__]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) } __attribute__((packed)) name__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * i915_context_engines_bond:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) * Constructed bonded pairs for execution within a virtual engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) * All engines are equal, but some are more equal than others. Given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) * the distribution of resources in the HW, it may be preferable to run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) * a request on a given subset of engines in parallel to a request on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) * specific engine. We enable this selection of engines within a virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) * engine by specifying bonding pairs, for any given master engine we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) * only execute on one of the corresponding siblings within the virtual engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) * To execute a request in parallel on the master engine and a sibling requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) * coordination with a I915_EXEC_FENCE_SUBMIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) struct i915_context_engines_bond {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) struct i915_user_extension base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) struct i915_engine_class_instance master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) __u16 num_bonds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) __u64 flags; /* all undefined flags must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) __u64 mbz64[4]; /* reserved for future use; must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) struct i915_engine_class_instance engines[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct i915_user_extension base; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct i915_engine_class_instance master; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) __u16 virtual_index; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) __u16 num_bonds; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) __u64 flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) __u64 mbz64[4]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct i915_engine_class_instance engines[N__]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) } __attribute__((packed)) name__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) struct i915_context_param_engines {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) __u64 extensions; /* linked chain of extension blocks, 0 terminates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) struct i915_engine_class_instance engines[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) __u64 extensions; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) struct i915_engine_class_instance engines[N__]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) } __attribute__((packed)) name__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) struct drm_i915_gem_context_create_ext_setparam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define I915_CONTEXT_CREATE_EXT_SETPARAM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) struct i915_user_extension base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) struct drm_i915_gem_context_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) struct drm_i915_gem_context_create_ext_clone {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) #define I915_CONTEXT_CREATE_EXT_CLONE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) struct i915_user_extension base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) __u32 clone_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define I915_CONTEXT_CLONE_ENGINES (1u << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define I915_CONTEXT_CLONE_FLAGS (1u << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define I915_CONTEXT_CLONE_SSEU (1u << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define I915_CONTEXT_CLONE_VM (1u << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) __u64 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) struct drm_i915_gem_context_destroy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) __u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) * DRM_I915_GEM_VM_CREATE -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) * Create a new virtual memory address space (ppGTT) for use within a context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) * on the same file. Extensions can be provided to configure exactly how the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * address space is setup upon creation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * returned in the outparam @id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) * No flags are defined, with all bits reserved and must be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) * An extension chain maybe provided, starting with @extensions, and terminated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) * by the @next_extension being 0. Currently, no extensions are defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) * DRM_I915_GEM_VM_DESTROY -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) * Destroys a previously created VM id, specified in @id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) * No extensions or flags are allowed currently, and so must be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) struct drm_i915_gem_vm_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) __u64 extensions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) __u32 vm_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) struct drm_i915_reg_read {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * Register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * For 64bit wide registers where the upper 32bits don't immediately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * follow the lower 32bits, the offset of the lower 32bits must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * be specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #define I915_REG_READ_8B_WA (1ul << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) __u64 val; /* Return value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* Known registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) * Render engine timestamp - 0x2358 + 64bit - gen7+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) * - Note this register returns an invalid value if using the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) * single instruction 8byte read, in order to workaround that pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) * flag I915_REG_READ_8B_WA in offset field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) struct drm_i915_reset_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) __u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) /* All resets since boot/module reload, for all contexts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) __u32 reset_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /* Number of batches lost when active in GPU, for this context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) __u32 batch_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) /* Number of batches lost pending for execution, for this context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) __u32 batch_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) struct drm_i915_gem_userptr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) __u64 user_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) __u64 user_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define I915_USERPTR_READ_ONLY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) * Returned handle for the object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) * Object handles are nonzero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) enum drm_i915_oa_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) I915_OA_FORMAT_A13 = 1, /* HSW only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) I915_OA_FORMAT_A29, /* HSW only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) I915_OA_FORMAT_A13_B8_C8, /* HSW only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) I915_OA_FORMAT_B4_C8, /* HSW only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) I915_OA_FORMAT_A45_B8_C8, /* HSW only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) I915_OA_FORMAT_B4_C8_A16, /* HSW only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) I915_OA_FORMAT_C4_B8, /* HSW+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* Gen8+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) I915_OA_FORMAT_A12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) I915_OA_FORMAT_A12_B8_C8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) I915_OA_FORMAT_A32u40_A4u32_B8_C8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) I915_OA_FORMAT_MAX /* non-ABI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) enum drm_i915_perf_property_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) * Open the stream for a specific context handle (as used with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) * execbuffer2). A stream opened for a specific context this way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) * won't typically require root privileges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) * This property is available in perf revision 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) DRM_I915_PERF_PROP_CTX_HANDLE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) * A value of 1 requests the inclusion of raw OA unit reports as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) * part of stream samples.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * This property is available in perf revision 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) DRM_I915_PERF_PROP_SAMPLE_OA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) * The value specifies which set of OA unit metrics should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) * configured, defining the contents of any OA unit reports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) * This property is available in perf revision 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) DRM_I915_PERF_PROP_OA_METRICS_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) * The value specifies the size and layout of OA unit reports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) * This property is available in perf revision 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) DRM_I915_PERF_PROP_OA_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * Specifying this property implicitly requests periodic OA unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) * sampling and (at least on Haswell) the sampling frequency is derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) * from this exponent as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * 80ns * 2^(period_exponent + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * This property is available in perf revision 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) DRM_I915_PERF_PROP_OA_EXPONENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) * Specifying this property is only valid when specify a context to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) * will hold preemption of the particular context we want to gather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) * performance data about. The execbuf2 submissions must include a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * This property is available in perf revision 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) DRM_I915_PERF_PROP_HOLD_PREEMPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) * Specifying this pins all contexts to the specified SSEU power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) * configuration for the duration of the recording.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) * This parameter's value is a pointer to a struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) * drm_i915_gem_context_param_sseu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * This property is available in perf revision 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) DRM_I915_PERF_PROP_GLOBAL_SSEU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) * This optional parameter specifies the timer interval in nanoseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * at which the i915 driver will check the OA buffer for available data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) * Minimum allowed value is 100 microseconds. A default value is used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) * the driver if this parameter is not specified. Note that larger timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) * values will reduce cpu consumption during OA perf captures. However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) * excessively large values would potentially result in OA buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) * overwrites as captures reach end of the OA buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) * This property is available in perf revision 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) DRM_I915_PERF_PROP_POLL_OA_PERIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) DRM_I915_PERF_PROP_MAX /* non-ABI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) struct drm_i915_perf_open_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) #define I915_PERF_FLAG_DISABLED (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) /** The number of u64 (id, value) pairs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) __u32 num_properties;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) * Pointer to array of u64 (id, value) pairs configuring the stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) * to open.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) __u64 properties_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) * Enable data capture for a stream that was either opened in a disabled state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) * via I915_PERF_FLAG_DISABLED or was later disabled via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) * I915_PERF_IOCTL_DISABLE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) * It is intended to be cheaper to disable and enable a stream than it may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) * to close and re-open a stream with the same configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) * It's undefined whether any pending data for the stream will be lost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) * This ioctl is available in perf revision 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) * Disable data capture for a stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) * It is an error to try and read a stream that is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) * This ioctl is available in perf revision 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) * Change metrics_set captured by a stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) * If the stream is bound to a specific context, the configuration change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) * will performed inline with that context such that it takes effect before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) * the next execbuf submission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) * Returns the previously bound metrics set id, or a negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) * This ioctl is available in perf revision 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) * Common to all i915 perf records
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) struct drm_i915_perf_record_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) __u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) __u16 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) __u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) enum drm_i915_perf_record_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) * Samples are the work horse record type whose contents are extensible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) * and defined when opening an i915 perf stream based on the given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) * properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) * Boolean properties following the naming convention
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) * every sample.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) * The order of these sample properties given by userspace has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) * affect on the ordering of data within a sample. The order is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) * documented here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) * struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) * struct drm_i915_perf_record_header header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) DRM_I915_PERF_RECORD_SAMPLE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) * Indicates that one or more OA reports were not written by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) * command collides with periodic sampling - which would be more likely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) * at higher sampling frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) * An error occurred that resulted in all pending OA reports being lost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) DRM_I915_PERF_RECORD_MAX /* non-ABI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) * Structure to upload perf dynamic configuration into the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) struct drm_i915_perf_oa_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) char uuid[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) __u32 n_mux_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) __u32 n_boolean_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) __u32 n_flex_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) * These fields are pointers to tuples of u32 values (register address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) * value). For example the expected length of the buffer pointed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) __u64 mux_regs_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) __u64 boolean_regs_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) __u64 flex_regs_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) struct drm_i915_query_item {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) __u64 query_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #define DRM_I915_QUERY_TOPOLOGY_INFO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) #define DRM_I915_QUERY_ENGINE_INFO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) #define DRM_I915_QUERY_PERF_CONFIG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) /* Must be kept compact -- no holes and well documented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) * When set to zero by userspace, this is filled with the size of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) * data to be written at the data_ptr pointer. The kernel sets this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) * value to a negative value to signal an error on a particular query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) * item.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) __s32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) * following :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) * - DRM_I915_QUERY_PERF_CONFIG_LIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) #define DRM_I915_QUERY_PERF_CONFIG_LIST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) * Data will be written at the location pointed by data_ptr when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) * value of length matches the length of the data to be written by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) * kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) __u64 data_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) struct drm_i915_query {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) __u32 num_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * Unused for now. Must be cleared to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) * This points to an array of num_items drm_i915_query_item structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) __u64 items_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) * data: contains the 3 pieces of information :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * - the slice mask with one bit per slice telling whether a slice is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * available. The availability of slice X can be queried with the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) * formula :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) * (data[X / 8] >> (X % 8)) & 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) * - the subslice mask for each slice with one bit per subslice telling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) * whether a subslice is available. Gen12 has dual-subslices, which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) * similar to two gen11 subslices. For gen12, this array represents dual-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) * subslices. The availability of subslice Y in slice X can be queried
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) * with the following formula :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) * (data[subslice_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) * X * subslice_stride +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) * Y / 8] >> (Y % 8)) & 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) * - the EU mask for each subslice in each slice with one bit per EU telling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) * whether an EU is available. The availability of EU Z in subslice Y in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) * slice X can be queried with the following formula :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) * (data[eu_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) * (X * max_subslices + Y) * eu_stride +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) * Z / 8] >> (Z % 8)) & 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) struct drm_i915_query_topology_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) * Unused for now. Must be cleared to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) __u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) __u16 max_slices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) __u16 max_subslices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) __u16 max_eus_per_subslice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) * Offset in data[] at which the subslice masks are stored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) __u16 subslice_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) * Stride at which each of the subslice masks for each slice are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) * stored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) __u16 subslice_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) * Offset in data[] at which the EU masks are stored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) __u16 eu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * Stride at which each of the EU masks for each subslice are stored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) __u16 eu_stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) __u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) * struct drm_i915_engine_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) * Describes one engine and it's capabilities as known to the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) struct drm_i915_engine_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) /** Engine class and instance. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) struct i915_engine_class_instance engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) /** Reserved field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) __u32 rsvd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) /** Engine flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) __u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) /** Capabilities of this engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) __u64 capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) /** Reserved fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) __u64 rsvd1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) * struct drm_i915_query_engine_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) * Engine info query enumerates all engines known to the driver by filling in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) * an array of struct drm_i915_engine_info structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) struct drm_i915_query_engine_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) /** Number of struct drm_i915_engine_info structs following. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) __u32 num_engines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) /** MBZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) __u32 rsvd[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) /** Marker for drm_i915_engine_info structures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) struct drm_i915_engine_info engines[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) struct drm_i915_query_perf_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) * this fields to the number of configurations available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) __u64 n_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) * i915 will use the value in this field as configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) * identifier to decide what data to write into config_ptr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) __u64 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) * i915 will use the value in this field as configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) * identifier to decide what data to write into config_ptr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) * String formatted like "%08x-%04x-%04x-%04x-%012x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) char uuid[36];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) * Unused for now. Must be cleared to zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) * write an array of __u64 of configuration identifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) * write a struct drm_i915_perf_oa_config. If the following fields of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) * drm_i915_perf_oa_config are set not set to 0, i915 will write into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) * the associated pointers the values of submitted when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) * configuration was created :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) * - n_mux_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) * - n_boolean_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) * - n_flex_regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) __u8 data[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) #endif /* _UAPI_I915_DRM_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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