^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* exynos_drm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2011 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Inki Dae <inki.dae@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Joonyoung Shim <jy0922.shim@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Seung-Woo Kim <sw0312.kim@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef _UAPI_EXYNOS_DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define _UAPI_EXYNOS_DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * User-desired buffer creation information structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @size: user-desired memory allocation size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - this size value would be page-aligned internally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @flags: user request for setting memory type or cache attributes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @handle: returned a handle to created gem object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - this handle will be set by gem module of kernel side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct drm_exynos_gem_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * A structure for getting a fake-offset that can be used with mmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @handle: handle of gem object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @reserved: just padding to be 64-bit aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @offset: a fake-offset of gem object.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct drm_exynos_gem_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * A structure to gem information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @handle: a handle to gem object created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @flags: flag value including memory type and cache attribute and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * this value would be set by driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @size: size to memory region allocated by gem and this size would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * be set by driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct drm_exynos_gem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * A structure for user connection request of virtual display.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @connection: indicate whether doing connection or not by user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @extensions: if this value is 1 then the vidi driver would need additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * 128bytes edid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @edid: the edid data pointer from user side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct drm_exynos_vidi_connection {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __u32 connection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __u32 extensions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __u64 edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* memory type definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum e_drm_exynos_gem_mem_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Physically Continuous memory and used as default. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) EXYNOS_BO_CONTIG = 0 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Physically Non-Continuous memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) EXYNOS_BO_NONCONTIG = 1 << 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* non-cachable mapping and used as default. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) EXYNOS_BO_NONCACHABLE = 0 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* cachable mapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) EXYNOS_BO_CACHABLE = 1 << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* write-combine mapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) EXYNOS_BO_WC = 1 << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) EXYNOS_BO_WC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct drm_exynos_g2d_get_ver {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __u32 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __u32 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct drm_exynos_g2d_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum drm_exynos_g2d_buf_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) G2D_BUF_USERPTR = 1 << 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum drm_exynos_g2d_event_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) G2D_EVENT_NOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) G2D_EVENT_NONSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) G2D_EVENT_STOP, /* not yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct drm_exynos_g2d_userptr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long userptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct drm_exynos_g2d_set_cmdlist {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __u64 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __u64 cmd_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __u32 cmd_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __u32 cmd_buf_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* for g2d event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __u64 event_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __u64 user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct drm_exynos_g2d_exec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __u64 async;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Exynos DRM IPP v2 API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Enumerate available IPP hardware modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @count_ipps: size of ipp_id array / number of ipp modules (set by driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @reserved: padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @ipp_id_ptr: pointer to ipp_id array or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct drm_exynos_ioctl_ipp_get_res {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __u32 count_ipps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __u64 ipp_id_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) enum drm_exynos_ipp_format_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DRM_EXYNOS_IPP_FORMAT_SOURCE = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DRM_EXYNOS_IPP_FORMAT_DESTINATION = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct drm_exynos_ipp_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) __u32 fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __u64 modifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) enum drm_exynos_ipp_capability {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DRM_EXYNOS_IPP_CAP_CROP = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) DRM_EXYNOS_IPP_CAP_ROTATE = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DRM_EXYNOS_IPP_CAP_SCALE = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DRM_EXYNOS_IPP_CAP_CONVERT = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Get IPP hardware capabilities and supported image formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @ipp_id: id of IPP module to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @capabilities: bitmask of drm_exynos_ipp_capability (set by driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @reserved: padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @formats_count: size of formats array (in entries) / number of filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * formats (set by driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @formats_ptr: pointer to formats array or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct drm_exynos_ioctl_ipp_get_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __u32 ipp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __u32 capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __u32 formats_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __u64 formats_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum drm_exynos_ipp_limit_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* size (horizontal/vertial) limits, in pixels (min, max, alignment) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* scale ratio (horizonta/vertial), 16.16 fixed point (min, max) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* image buffer area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER = 0x0001 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* src/dst rectangle area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) DRM_EXYNOS_IPP_LIMIT_SIZE_AREA = 0x0002 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* src/dst rectangle area when rotation enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED = 0x0003 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DRM_EXYNOS_IPP_LIMIT_TYPE_MASK = 0x000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DRM_EXYNOS_IPP_LIMIT_SIZE_MASK = 0x000f << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct drm_exynos_ipp_limit_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __u32 min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __u32 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __u32 align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * IPP module limitation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @type: limit type (see drm_exynos_ipp_limit_type enum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @reserved: padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @h: horizontal limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @v: vertical limits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct drm_exynos_ipp_limit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct drm_exynos_ipp_limit_val h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct drm_exynos_ipp_limit_val v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Get IPP limits for given image format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @ipp_id: id of IPP module to query
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @fourcc: image format code (see DRM_FORMAT_* in drm_fourcc.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @modifier: image format modifier (see DRM_FORMAT_MOD_* in drm_fourcc.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @type: source/destination identifier (drm_exynos_ipp_format_flag enum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @limits_count: size of limits array (in entries) / number of filled entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * (set by driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @limits_ptr: pointer to limits array or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct drm_exynos_ioctl_ipp_get_limits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __u32 ipp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) __u32 fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __u64 modifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) __u32 limits_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __u64 limits_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) enum drm_exynos_ipp_task_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* buffer described by struct drm_exynos_ipp_task_buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) DRM_EXYNOS_IPP_TASK_BUFFER = 0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* rectangle described by struct drm_exynos_ipp_task_rect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DRM_EXYNOS_IPP_TASK_RECTANGLE = 0x0002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* transformation described by struct drm_exynos_ipp_task_transform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DRM_EXYNOS_IPP_TASK_TRANSFORM = 0x0003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* alpha configuration described by struct drm_exynos_ipp_task_alpha */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DRM_EXYNOS_IPP_TASK_ALPHA = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* source image data (for buffer and rectangle chunks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DRM_EXYNOS_IPP_TASK_TYPE_SOURCE = 0x0001 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* destination image data (for buffer and rectangle chunks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION = 0x0002 << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Memory buffer with image data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @id: must be DRM_EXYNOS_IPP_TASK_BUFFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * other parameters are same as for AddFB2 generic DRM ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct drm_exynos_ipp_task_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __u32 fourcc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __u32 width, height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __u32 gem_id[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) __u32 offset[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __u32 pitch[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __u64 modifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Rectangle for processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @id: must be DRM_EXYNOS_IPP_TASK_RECTANGLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @reserved: padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @x,@y: left corner in pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @w,@h: width/height in pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct drm_exynos_ipp_task_rect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __u32 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __u32 y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) __u32 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __u32 h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Image tranformation description.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @id: must be DRM_EXYNOS_IPP_TASK_TRANSFORM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @rotation: DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct drm_exynos_ipp_task_transform {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) __u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) __u32 rotation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Image global alpha configuration for formats without alpha values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @id: must be DRM_EXYNOS_IPP_TASK_ALPHA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @value: global alpha value (0-255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct drm_exynos_ipp_task_alpha {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) __u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) enum drm_exynos_ipp_flag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* generate DRM event after processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DRM_EXYNOS_IPP_FLAG_EVENT = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* dry run, only check task parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) DRM_EXYNOS_IPP_FLAG_TEST_ONLY = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* non-blocking processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DRM_EXYNOS_IPP_FLAG_NONBLOCK = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Perform image processing described by array of drm_exynos_ipp_task_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * structures (parameters array).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * @ipp_id: id of IPP module to run the task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * @flags: bitmask of drm_exynos_ipp_flag values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * @reserved: padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * @params_size: size of parameters array (in bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @params_ptr: pointer to parameters array or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @user_data: (optional) data for drm event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct drm_exynos_ioctl_ipp_commit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) __u32 ipp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) __u32 params_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __u64 params_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) __u64 user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DRM_EXYNOS_GEM_CREATE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DRM_EXYNOS_GEM_MAP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DRM_EXYNOS_GEM_GET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DRM_EXYNOS_VIDI_CONNECTION 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* G2D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define DRM_EXYNOS_G2D_GET_VER 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DRM_EXYNOS_G2D_EXEC 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* IPP - Image Post Processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DRM_EXYNOS_IPP_GET_RESOURCES 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define DRM_EXYNOS_IPP_GET_CAPS 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DRM_EXYNOS_IPP_GET_LIMITS 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define DRM_EXYNOS_IPP_COMMIT 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DRM_EXYNOS_IPP_GET_RESOURCES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct drm_exynos_ioctl_ipp_get_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define DRM_IOCTL_EXYNOS_IPP_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DRM_EXYNOS_IPP_GET_LIMITS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct drm_exynos_ioctl_ipp_get_limits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DRM_IOCTL_EXYNOS_IPP_COMMIT DRM_IOWR(DRM_COMMAND_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Exynos specific events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define DRM_EXYNOS_G2D_EVENT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define DRM_EXYNOS_IPP_EVENT 0x80000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct drm_exynos_g2d_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct drm_event base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) __u64 user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __u32 tv_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) __u32 tv_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __u32 cmdlist_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) __u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct drm_exynos_ipp_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct drm_event base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) __u64 user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __u32 tv_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) __u32 tv_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) __u32 ipp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __u32 sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) __u64 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #endif /* _UAPI_EXYNOS_DRM_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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