^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Etnaviv Project
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * under the terms of the GNU General Public License version 2 as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is distributed in the hope that it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * You should have received a copy of the GNU General Public License along with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * this program. If not, see <http://www.gnu.org/licenses/>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __ETNAVIV_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __ETNAVIV_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Please note that modifications to all structs defined here are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * subject to backwards-compatibility constraints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * user/kernel compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 2) Keep fields aligned to their size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 3) Because of how drm_ioctl() works, we can add new fields at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * the end of an ioctl if some care is taken: drm_ioctl() will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * zero out the new fields at the tail of the ioctl, so a zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * value should have a backwards compatible meaning. And for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * output params, userspace won't see the newly added output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * fields.. so that has to be somehow ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* timeouts are specified in clock-monotonic absolute times (to simplify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * restarting interrupted ioctls). The following struct is logically the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * same as 'struct timespec' but 32/64b ABI safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct drm_etnaviv_timespec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __s64 tv_sec; /* seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) __s64 tv_nsec; /* nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ETNAVIV_PARAM_GPU_MODEL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ETNAVIV_PARAM_GPU_REVISION 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ETNA_MAX_PIPES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct drm_etnaviv_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __u32 pipe; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __u32 param; /* in, ETNAVIV_PARAM_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __u64 value; /* out (get_param) or in (set_param) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * GEM buffers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ETNA_BO_CACHE_MASK 0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* cache modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ETNA_BO_CACHED 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ETNA_BO_WC 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ETNA_BO_UNCACHED 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* map flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ETNA_BO_FORCE_MMU 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct drm_etnaviv_gem_new {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __u64 size; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __u32 flags; /* in, mask of ETNA_BO_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __u32 handle; /* out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct drm_etnaviv_gem_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __u32 handle; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __u64 offset; /* out, offset to pass to mmap() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ETNA_PREP_READ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ETNA_PREP_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ETNA_PREP_NOSYNC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct drm_etnaviv_gem_cpu_prep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __u32 handle; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __u32 op; /* in, mask of ETNA_PREP_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct drm_etnaviv_timespec timeout; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct drm_etnaviv_gem_cpu_fini {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __u32 handle; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __u32 flags; /* in, placeholder for now, no defined values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Cmdstream Submission:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* The value written into the cmdstream is logically:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * relocbuf->gpuaddr + reloc_offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * NOTE that reloc's must be sorted by order of increasing submit_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * otherwise EINVAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct drm_etnaviv_gem_submit_reloc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __u32 submit_offset; /* in, offset from submit_bo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __u32 reloc_idx; /* in, index of reloc_bo buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __u64 reloc_offset; /* in, offset from start of reloc_bo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __u32 flags; /* in, placeholder for now, no defined values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * cmdstream buffer(s) themselves or reloc entries) has one (and only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * one) entry in the submit->bos[] table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * As a optimization, the current buffer (gpu virtual address) can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * passed back through the 'presumed' field. If on a subsequent reloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * userspace passes back a 'presumed' address that is still valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * then patching the cmdstream for this entry is skipped. This can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * avoid kernel needing to map/access the cmdstream bo in the common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * If the submit is a softpin submit (ETNA_SUBMIT_SOFTPIN) the 'presumed'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * field is interpreted as the fixed location to map the bo into the gpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * virtual address space. If the kernel is unable to map the buffer at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * this location the submit will fail. This means userspace is responsible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * for the whole gpu virtual address management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ETNA_SUBMIT_BO_READ 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ETNA_SUBMIT_BO_WRITE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct drm_etnaviv_gem_submit_bo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) __u32 flags; /* in, mask of ETNA_SUBMIT_BO_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __u32 handle; /* in, GEM handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __u64 presumed; /* in/out, presumed buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* performance monitor request (pmr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ETNA_PM_PROCESS_PRE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ETNA_PM_PROCESS_POST 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct drm_etnaviv_gem_submit_pmr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __u32 flags; /* in, when to process request (ETNA_PM_PROCESS_x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __u8 domain; /* in, pm domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __u16 signal; /* in, pm signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __u32 sequence; /* in, sequence number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __u32 read_offset; /* in, offset from read_bo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) __u32 read_idx; /* in, index of read_bo buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Each cmdstream submit consists of a table of buffers involved, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * one or more cmdstream buffers. This allows for conditional execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * (context-restore), and IB buffers needed for per tile/bin draw cmds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ETNA_SUBMIT_NO_IMPLICIT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ETNA_SUBMIT_FENCE_FD_IN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ETNA_SUBMIT_SOFTPIN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ETNA_SUBMIT_FENCE_FD_IN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ETNA_SUBMIT_FENCE_FD_OUT| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ETNA_SUBMIT_SOFTPIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ETNA_PIPE_3D 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ETNA_PIPE_2D 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ETNA_PIPE_VG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct drm_etnaviv_gem_submit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __u32 fence; /* out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __u32 pipe; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __u32 exec_state; /* in, initial execution state (ETNA_PIPE_x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __u32 nr_bos; /* in, number of submit_bo's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) __u32 nr_relocs; /* in, number of submit_reloc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __u32 stream_size; /* in, cmdstream size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __u64 bos; /* in, ptr to array of submit_bo's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __u64 relocs; /* in, ptr to array of submit_reloc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __u64 stream; /* in, ptr to cmdstream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __u32 flags; /* in, mask of ETNA_SUBMIT_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __u64 pmrs; /* in, ptr to array of submit_pmr's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __u32 nr_pmrs; /* in, number of submit_pmr's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* The normal way to synchronize with the GPU is just to CPU_PREP on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * a buffer if you need to access it from the CPU (other cmdstream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * handle the required synchronization under the hood). This ioctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * mainly just exists as a way to implement the gallium pipe_fence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * APIs without requiring a dummy bo to synchronize on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ETNA_WAIT_NONBLOCK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct drm_etnaviv_wait_fence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __u32 pipe; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __u32 fence; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __u32 flags; /* in, mask of ETNA_WAIT_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct drm_etnaviv_timespec timeout; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ETNA_USERPTR_READ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ETNA_USERPTR_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct drm_etnaviv_gem_userptr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __u64 user_ptr; /* in, page aligned user pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) __u64 user_size; /* in, page aligned user size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) __u32 flags; /* in, flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) __u32 handle; /* out, non-zero handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct drm_etnaviv_gem_wait {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __u32 pipe; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __u32 handle; /* in, bo to be waited for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __u32 flags; /* in, mask of ETNA_WAIT_x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct drm_etnaviv_timespec timeout; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Performance Monitor (PM):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct drm_etnaviv_pm_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) __u32 pipe; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __u8 iter; /* in/out, select pm domain at index iter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __u8 id; /* out, id of domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __u16 nr_signals; /* out, how many signals does this domain provide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) char name[64]; /* out, name of domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct drm_etnaviv_pm_signal {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __u32 pipe; /* in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __u8 domain; /* in, pm domain index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __u16 iter; /* in/out, select pm source at index iter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __u16 id; /* out, id of signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) char name[64]; /* out, name of domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DRM_ETNAVIV_GET_PARAM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* placeholder:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DRM_ETNAVIV_SET_PARAM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DRM_ETNAVIV_GEM_NEW 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DRM_ETNAVIV_GEM_INFO 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DRM_ETNAVIV_GEM_CPU_PREP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DRM_ETNAVIV_GEM_CPU_FINI 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DRM_ETNAVIV_GEM_SUBMIT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DRM_ETNAVIV_WAIT_FENCE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DRM_ETNAVIV_GEM_USERPTR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DRM_ETNAVIV_GEM_WAIT 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DRM_ETNAVIV_NUM_IOCTLS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif /* __ETNAVIV_DRM_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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