^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2011 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The above copyright notice and this permission notice (including the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * paragraph) shall be included in all copies or substantial portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifndef DRM_FOURCC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRM_FOURCC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DOC: overview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * In the DRM subsystem, framebuffer pixel formats are described using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * fourcc code, a Format Modifier may optionally be provided, in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * further describe the buffer's format - for example tiling or compression.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Format Modifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * ----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Format modifiers are used in conjunction with a fourcc code, forming a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * unique fourcc:modifier pair. This format:modifier pair must fully define the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * format and data layout of the buffer, and should be the only way to describe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * that particular buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Having multiple fourcc:modifier pairs which describe the same layout should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * be avoided, as such aliases run the risk of different drivers exposing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * different names for the same data format, forcing userspace to understand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * that they are aliases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Format modifiers may change any property of the buffer, including the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * of planes and/or the required allocation size. Format modifiers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * vendor-namespaced, and as such the relationship between a fourcc code and a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * modifier is specific to the modifer being used. For example, some modifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * may preserve meaning - such as number of planes - from the fourcc code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * whereas others may not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Vendors should document their modifier usage in as much detail as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * possible, to ensure maximum compatibility across devices, drivers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * applications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * The authoritative list of format modifier codes is found in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * `include/uapi/drm/drm_fourcc.h`
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ((__u32)(c) << 16) | ((__u32)(d) << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Reserve 0 for the invalid format specifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DRM_FORMAT_INVALID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* color index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 8 bpp Red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* 16 bpp Red */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* 16 bpp RG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* 32 bpp RG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* 8 bpp RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* 16 bpp RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* 24 bpp RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* 32 bpp RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Floating point 64bpp RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * IEEE 754-2008 binary16 half-precision float
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * [15:0] sign:exponent:mantissa 1:5:10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* packed YCbCr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * packed Y2xx indicate for each component, xx valid data occupy msb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * 16-xx padding occupy lsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * packed Y4xx indicate for each component, xx valid data occupy msb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * 16-xx padding occupy lsb except Y410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * packed YCbCr420 2x2 tiled formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * 1-plane YUV 4:2:0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * In these formats, the component ordering is specified (Y, followed by U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * then V), but the exact Linear layout is undefined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * These formats can only be used with a non-Linear modifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * 2 plane RGB + A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * index 0 = RGB plane, same format as the corresponding non _A8 format has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * index 1 = A plane, [7:0] A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * 2 plane YCbCr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * index 0 = Y plane, [7:0] Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * 2 plane YCbCr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * 2 plane YCbCr MSB aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * index 0 = Y plane, [15:0] Y:x [10:6] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * 2 plane YCbCr MSB aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * index 0 = Y plane, [15:0] Y:x [10:6] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * 2 plane YCbCr MSB aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * index 0 = Y plane, [15:0] Y:x [12:4] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * 2 plane YCbCr MSB aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * index 0 = Y plane, [15:0] Y little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* 3 plane non-subsampled (444) YCbCr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * 16 bits per component, but only 10 bits are used and 6 bits are padded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * index 0: Y plane, [15:0] Y:x [10:6] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* 3 plane non-subsampled (444) YCrCb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * 16 bits per component, but only 10 bits are used and 6 bits are padded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * index 0: Y plane, [15:0] Y:x [10:6] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * 3 plane YCbCr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * index 0: Y plane, [7:0] Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * index 1: Cb plane, [7:0] Cb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * index 2: Cr plane, [7:0] Cr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * index 1: Cr plane, [7:0] Cr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * index 2: Cb plane, [7:0] Cb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Format Modifiers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Format modifiers describe, typically, a re-ordering or modification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * of the data in a plane of an FB. This can be used to express tiled/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * swizzled formats, or compression, or a combination of the two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * The upper 8 bits of the format modifier are a vendor-id as assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * below. The lower 56 bits are assigned as vendor sees fit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Vendor Ids: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define DRM_FORMAT_MOD_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define DRM_FORMAT_MOD_VENDOR_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DRM_FORMAT_MOD_VENDOR_ROCKCHIP 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* add more to the end as needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define fourcc_mod_code(vendor, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Format Modifier tokens:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * When adding a new token please document the layout with a code comment,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * similar to the fourcc codes above. drm_fourcc.h is considered the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * authoritative source for all of these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Generic modifier names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * for layouts which are common across multiple vendors. To preserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * compatibility, in cases where a vendor-specific definition already exists and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * a generic name for it is desired, the common name is a purely symbolic alias
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * and must use the same numerical value as the original definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * Note that generic names should only be used for modifiers which describe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * generic layouts (such as pixel re-ordering), which may have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * independently-developed support across multiple vendors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * In future cases where a generic layout is identified before merging with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * 'NONE' could be considered. This should only be for obvious, exceptional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * apply to a single vendor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Generic names should not be used for cases where multiple hardware vendors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * have implementations of the same standardised compression scheme (such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * AFBC). In those cases, all implementations should use the same format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * modifier(s), reflecting the vendor of the standard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Invalid Modifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * This modifier can be used as a sentinel to terminate the format modifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * list, or to initialize a variable with an invalid modifier. It might also be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * used to report an error back to userspace for certain APIs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * Linear Layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * Just plain linear layout. Note that this is different from no specifying any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * which tells the driver to also take driver-internal information into account
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * and so might actually result in a tiled framebuffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Intel framebuffer modifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Intel X-tiling layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * in row-major layout. Within the tile bytes are laid out row-major, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * a platform-dependent stride. On top of that the memory can apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * platform-depending swizzling of some higher address bits into bit6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * On earlier platforms the is highly platforms specific and not useful for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * cross-driver sharing. It exists since on a given platform it does uniquely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * identify the layout in a simple way for i915-specific userspace, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * facilitated conversion of userspace to modifiers. Additionally the exact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * format on some really old platforms is not known.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Intel Y-tiling layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * chunks column-major, with a platform-dependent height. On top of that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * memory can apply platform-depending swizzling of some higher address bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * into bit6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * On earlier platforms the is highly platforms specific and not useful for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * cross-driver sharing. It exists since on a given platform it does uniquely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * identify the layout in a simple way for i915-specific userspace, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * facilitated conversion of userspace to modifiers. Additionally the exact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * format on some really old platforms is not known.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * Intel Yf-tiling layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * This is a tiled layout using 4Kb tiles in row-major layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * are arranged in four groups (two wide, two high) with column-major layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Each group therefore consits out of four 256 byte units, which are also laid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * out as 2x2 column-major.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * 256 byte units are made out of four 64 byte blocks of pixels, producing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * either a square block or a 2:1 unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * in pixel depends on the pixel depth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Intel color control surface (CCS) for render compression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * The framebuffer format must be one of the 8:8:8:8 RGB formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * The main surface will be plane index 0 and must be Y/Yf-tiled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * the CCS will be plane index 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Each CCS tile matches a 1024x512 pixel area of the main surface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * To match certain aspects of the 3D hardware the CCS is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * considered to be made up of normal 128Bx32 Y tiles, Thus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * the CCS pitch must be specified in multiples of 128 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * But that fact is not relevant unless the memory is accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * Intel color control surfaces (CCS) for Gen-12 render compression.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * The main surface is Y-tiled and at plane index 0, the CCS is linear and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * main surface. In other words, 4 bits in CCS map to a main surface cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * line pair. The main surface pitch is required to be a multiple of four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Y-tile widths.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Intel color control surfaces (CCS) for Gen-12 media compression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * The main surface is Y-tiled and at plane index 0, the CCS is linear and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * main surface. In other words, 4 bits in CCS map to a main surface cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * line pair. The main surface pitch is required to be a multiple of four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * planes 2 and 3 for the respective CCS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * Macroblocks are laid in a Z-shape, and each pixel data is following the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * standard NV12 style.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * As for NV12, an image is the result of two frame buffers: one for Y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * Alignment requirements are (for each buffer):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * - multiple of 128 pixels for the width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * - multiple of 32 pixels for the height
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * layout. For YCbCr formats Cb/Cr components are taken in such a way that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * they correspond to their 16x16 luma block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * Qualcomm Compressed Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * Refers to a compressed variant of the base format that is compressed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Implementation may be platform and base-format specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Each macrotile consists of m x n (mostly 4 x 4) tiles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Pixel data pitch/stride is aligned with macrotile width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Pixel data height is aligned with macrotile height.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * Entire pixel data buffer is aligned with 4k(bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Vivante framebuffer modifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * Vivante 4x4 tiling layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * Vivante 64x64 super-tiling layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * major layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * For more information: see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * Vivante 4x4 tiling layout for dual-pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * different base address. Offsets from the base addresses are therefore halved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * compared to the non-split tiled layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * Vivante 64x64 super-tiling layout for dual-pipe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * starts at a different base address. Offsets from the base addresses are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * therefore halved compared to the non-split super-tiled layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* NVIDIA frame buffer modifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * Pixels are arranged in simple tiles of 16 x 16 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * and Tegra GPUs starting with Tegra K1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * based on the architecture generation. GOBs themselves are then arranged in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * a block depth or height of "4").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * in full detail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * Macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Bits Param Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * ---- ----- -----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * 3:0 h log2(height) of each block, in GOBs. Placed here for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * compatibility with the existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * compatibility with the existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * size). Must be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * Note there is no log2(width) parameter. Some portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * hardware support a block width of two gobs, but it is impractical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * to use due to lack of support elsewhere, and has no known
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * benefits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * 11:9 - Reserved (To support 2D-array textures with variable array stride
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * in blocks, specified via log2(tile width in blocks)). Must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * 19:12 k Page Kind. This value directly maps to a field in the page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * tables of all GPUs >= NV50. It affects the exact layout of bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * in memory and can be derived from the tuple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * (format, GPU model, compression type, samples per pixel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Where compression type is defined below. If GPU model were
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * implied by the format modifier, format, or memory buffer, page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * kind would not need to be included in the modifier itself, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * since the modifier should define the layout of the associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * memory buffer independent from any device or other context, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * must be included here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * starting with Fermi GPUs. Additionally, the mapping between page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * kind and bit layout has changed at various points.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * 2 = Gob Height 8, Turing+ Page Kind mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * 3 = Reserved for future use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * bit remapping step that occurs at an even lower level than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * page kind and block linear swizzles. This causes the layout of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * surfaces mapped in those SOC's GPUs to be incompatible with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * equivalent mapping on other GPUs in the same system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * 1 = Desktop GPU and Tegra Xavier+ Layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * 25:23 c Lossless Framebuffer Compression type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * 0 = none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * 1 = ROP/3D, layout 1, exact compression format implied by Page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * Kind field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * 2 = ROP/3D, layout 2, exact compression format implied by Page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * Kind field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * 3 = CDE horizontal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * 4 = CDE vertical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * 5 = Reserved for future use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * 6 = Reserved for future use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * 7 = Reserved for future use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * 55:25 - Reserved for future use. Must be zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) fourcc_mod_code(NVIDIA, (0x10 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ((h) & 0xf) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) (((k) & 0xff) << 12) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) (((g) & 0x3) << 20) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) (((s) & 0x1) << 22) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) (((c) & 0x7) << 23)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* To grandfather in prior block linear format modifiers to the above layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * with block-linear layouts, is remapped within drivers to the value 0xfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * which corresponds to the "generic" kind used for simple single-sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * uncompressed color formats on Fermi - Volta GPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static inline __u64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (!(modifier & 0x10) || (modifier & (0xff << 12)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return modifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return modifier | (0xfe << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * 16Bx2 Block Linear layout, used by Tegra K1 and later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * vertically by a power of 2 (1 to 32 GOBs) to form a block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * Valid values are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * 0 == ONE_GOB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * 1 == TWO_GOBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * 2 == FOUR_GOBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * 3 == EIGHT_GOBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * 4 == SIXTEEN_GOBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * 5 == THIRTYTWO_GOBS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * in full detail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * Some Broadcom modifiers take parameters, for example the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * vertical lines in the image. Reserve the lower 32 bits for modifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * type, and the next 24 bits for parameters. Top 8 bits are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * vendor code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define __fourcc_mod_broadcom_param_shift 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define __fourcc_mod_broadcom_param_bits 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define fourcc_mod_broadcom_code(val, params) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define fourcc_mod_broadcom_param(m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define fourcc_mod_broadcom_mod(m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) __fourcc_mod_broadcom_param_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * Broadcom VC4 "T" format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * This is the primary layout that the V3D GPU can texture from (it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * can't do linear). The T format has:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * pixels at 32 bit depth.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * 16x16 pixels).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * they're (TR, BR, BL, TL), where bottom left is start of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * tiles) or right-to-left (odd rows of 4k tiles).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Broadcom SAND format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * This is the native format that the H.264 codec block uses. For VC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * The image can be considered to be split into columns, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * columns are placed consecutively into memory. The width of those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * columns can be either 32, 64, 128, or 256 pixels, but in practice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * only 128 pixel columns are used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * The pitch between the start of each column is set to optimally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * switch between SDRAM banks. This is passed as the number of lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * of column width in the modifier (we can't use the stride value due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * to various core checks that look at it , so you should set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * stride to width*cpp).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * Note that the column height for this format modifier is the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * for all of the planes, assuming that each column contains both Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * and UV. Some SAND-using hardware stores UV in a separate tiled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * image from Y to reduce the column height, which is not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * with these modifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) fourcc_mod_broadcom_code(2, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) fourcc_mod_broadcom_code(3, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) fourcc_mod_broadcom_code(4, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) fourcc_mod_broadcom_code(5, v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* Broadcom UIF format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * This is the common format for the current Broadcom multimedia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * blocks, including V3D 3.x and newer, newer video codecs, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * displays.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * stored in columns, with padding between the columns to ensure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * moving from one column to the next doesn't hit the same SDRAM page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * To calculate the padding, it is assumed that each hardware block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * and the software driving it knows the platform's SDRAM page size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * number of banks, and XOR address, and that it's identical between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * all blocks using the format. This tiling modifier will use XOR as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * necessary to reduce the padding. If a hardware block can't do XOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * the assumption is that a no-XOR tiling modifier will be created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * Arm Framebuffer Compression (AFBC) modifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * AFBC is a proprietary lossless image compression protocol and format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * It provides fine-grained random access and minimizes the amount of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * transferred between IP blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * AFBC has several features which may be supported and/or used, which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * represented using bits in the modifier. Not all combinations are valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * and different devices or use-cases may support different combinations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * Further information on the use of AFBC modifiers can be found in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * Documentation/gpu/afbc.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * modifiers) denote the category for modifiers. Currently we have only two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * different categories.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * AFBC superblock size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * Indicates the superblock size(s) used for the AFBC buffer. The buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * size (in pixels) must be aligned to a multiple of the superblock size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * Four lowest significant bits(LSBs) are reserved for block size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Where one superblock size is specified, it applies to all planes of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * the first applies to the Luma plane and the second applies to the Chroma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * AFBC lossless colorspace transform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * Indicates that the buffer makes use of the AFBC lossless colorspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * transform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * AFBC block-split
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * Indicates that the payload of each superblock is split. The second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * half of the payload is positioned at a predefined offset from the start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * of the superblock payload.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * AFBC sparse layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) * This flag indicates that the payload of each superblock must be stored at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * predefined position relative to the other superblocks in the same AFBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * buffer. This order is the same order used by the header buffer. In this mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * each superblock is given the same amount of space as an uncompressed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * superblock of the particular format would require, rounding up to the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * multiple of 128 bytes in size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * AFBC copy-block restrict
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * Buffers with this flag must obey the copy-block restriction. The restriction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * is such that there are no copy-blocks referring across the border of 8x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * blocks. For the subsampled data the 8x8 limitation is also subsampled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * AFBC tiled layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * superblocks inside a tile are stored together in memory. 8x8 tiles are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * larger bpp formats. The order between the tiles is scan line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * When the tiled layout is used, the buffer size (in pixels) must be aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * to the tile size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * AFBC solid color blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * can be reduced if a whole superblock is a single color.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define AFBC_FORMAT_MOD_SC (1ULL << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * AFBC double-buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * Indicates that the buffer is allocated in a layout safe for front-buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * rendering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define AFBC_FORMAT_MOD_DB (1ULL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * AFBC buffer content hints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * Indicates that the buffer includes per-superblock content hints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* AFBC uncompressed storage mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * Indicates that the buffer is using AFBC uncompressed storage mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * In this mode all superblock payloads in the buffer use the uncompressed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * storage mode, which is usually only used for data which cannot be compressed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * The buffer layout is the same as for AFBC buffers without USM set, this only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * affects the storage mode of the individual superblocks. Note that even a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * buffer without USM set may use uncompressed storage mode for some or all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * superblocks, USM just guarantees it for all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define AFBC_FORMAT_MOD_USM (1ULL << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * Arm 16x16 Block U-Interleaved modifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * in the block are reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * Allwinner tiled modifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * This tiling mode is implemented by the VPU found on all Allwinner platforms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * planes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * With this tiling, the luminance samples are disposed in tiles representing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * The pixel order in each tile is linear and the tiles are disposed linearly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * both in row-major order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * Amlogic Video Framebuffer Compression modifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * Amlogic uses a proprietary lossless image compression protocol and format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * for their hardware video codec accelerators, either video decoders or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * video input encoders.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * It considerably reduces memory bandwidth while writing and reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * frames in memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * The underlying storage is considered to be 3 components, 8bit or 10-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * per component YCbCr 420, single plane :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * - DRM_FORMAT_YUV420_8BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * - DRM_FORMAT_YUV420_10BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * The first 8 bits of the mode defines the layout, then the following 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * defines the options changing the layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * Not all combinations are valid, and different SoCs may support different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * combinations of layout and options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define __fourcc_mod_amlogic_layout_mask 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define __fourcc_mod_amlogic_options_shift 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define __fourcc_mod_amlogic_options_mask 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) fourcc_mod_code(AMLOGIC, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ((__layout) & __fourcc_mod_amlogic_layout_mask) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) (((__options) & __fourcc_mod_amlogic_options_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) << __fourcc_mod_amlogic_options_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* Amlogic FBC Layouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * Amlogic FBC Basic Layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * The basic layout is composed of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * - a body content organized in 64x32 superblocks with 4096 bytes per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * superblock in default mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * - a 32 bytes per 128x64 header block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * This layout is transferrable between Amlogic SoCs supporting this modifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * Amlogic FBC Scatter Memory layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * Indicates the header contains IOMMU references to the compressed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * frames content to optimize memory access and layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * In this mode, only the header memory address is needed, thus the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * content memory organization is tied to the current producer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * execution and cannot be saved/dumped neither transferrable between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * Amlogic SoCs supporting this modifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * Due to the nature of the layout, these buffers are not expected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * be accessible by the user-space clients, but only accessible by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * hardware producers and consumers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * The user-space clients should expect a failure while trying to mmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * the DMA-BUF handle returned by the producer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* Amlogic FBC Layout Options Bit Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * Amlogic FBC Memory Saving mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * Indicates the storage is packed when pixel size is multiple of word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * boudaries, i.e. 8bit should be stored in this mode to save allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * This mode reduces body layout to 3072 bytes per 64x32 superblock with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * the basic layout and 3200 bytes per 64x32 superblock combined with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * the scatter layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define ROCKCHIP_TILED_BLOCK_SIZE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define ROCKCHIP_TILED_BLOCK_SIZE_8x8 (1ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0 (2ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE1 (3ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #define DRM_FORMAT_MOD_ROCKCHIP_TILED(_mode) fourcc_mod_code(ROCKCHIP, _mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define IS_ROCKCHIP_TILED_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_ROCKCHIP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #endif /* DRM_FOURCC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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