^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * \file drm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Header for the Direct Rendering Manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * \author Rickard E. (Rik) Faith <faith@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * \par Acknowledgments:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The above copyright notice and this permission notice (including the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * paragraph) shall be included in all copies or substantial portions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifndef _DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define _DRM_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #if defined(__KERNEL__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) typedef unsigned int drm_handle_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #elif defined(__linux__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) typedef unsigned int drm_handle_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #else /* One of the BSDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <stdint.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <sys/ioccom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <sys/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) typedef int8_t __s8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) typedef uint8_t __u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) typedef int16_t __s16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) typedef uint16_t __u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) typedef int32_t __s32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) typedef uint32_t __u32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) typedef int64_t __s64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) typedef uint64_t __u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) typedef size_t __kernel_size_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) typedef unsigned long drm_handle_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) typedef unsigned int drm_context_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) typedef unsigned int drm_drawable_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) typedef unsigned int drm_magic_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Cliprect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * \warning: If you change this structure, make sure you change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * XF86DRIClipRectRec in the server as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * \note KW: Actually it's illegal to change either for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * backwards-compatibility reasons.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct drm_clip_rect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned short x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned short y1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned short x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned short y2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Drawable information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct drm_drawable_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int num_rects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct drm_clip_rect *rects;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Texture region,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct drm_tex_region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned char next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned char prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned char in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned char padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int age;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Hardware lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * The lock structure is a simple cache-line aligned integer. To avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * processor bus contention on a multiprocessor system, there should not be any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * other data stored in the same cache line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct drm_hw_lock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __volatile__ unsigned int lock; /**< lock variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) char padding[60]; /**< Pad to cache line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * DRM_IOCTL_VERSION ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * \sa drmGetVersion().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct drm_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int version_major; /**< Major version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int version_minor; /**< Minor version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int version_patchlevel; /**< Patch level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __kernel_size_t name_len; /**< Length of name buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) char __user *name; /**< Name of driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __kernel_size_t date_len; /**< Length of date buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) char __user *date; /**< User-space buffer to hold date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __kernel_size_t desc_len; /**< Length of desc buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) char __user *desc; /**< User-space buffer to hold desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * DRM_IOCTL_GET_UNIQUE ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * \sa drmGetBusid() and drmSetBusId().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct drm_unique {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) __kernel_size_t unique_len; /**< Length of unique */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) char __user *unique; /**< Unique name for driver instantiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct drm_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int count; /**< Length of user-space structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct drm_version __user *version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct drm_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * DRM_IOCTL_CONTROL ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * \sa drmCtlInstHandler() and drmCtlUninstHandler().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct drm_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DRM_ADD_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DRM_RM_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DRM_INST_HANDLER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DRM_UNINST_HANDLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Type of memory to map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) enum drm_map_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) _DRM_REGISTERS = 1, /**< no caching, no core dump */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) _DRM_SHM = 2, /**< shared, cached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) _DRM_AGP = 3, /**< AGP/GART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Memory mapping flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) enum drm_map_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) _DRM_READ_ONLY = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) _DRM_LOCKED = 0x04, /**< shared, cached, locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) _DRM_KERNEL = 0x08, /**< kernel requires access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) _DRM_REMOVABLE = 0x40, /**< Removable mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) _DRM_DRIVER = 0x80 /**< Managed by driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct drm_ctx_priv_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned int ctx_id; /**< Context requesting private mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) void *handle; /**< Handle of map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * \sa drmAddMap().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct drm_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long offset; /**< Requested physical address (0 for SAREA)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long size; /**< Requested physical size (bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) enum drm_map_type type; /**< Type of memory to map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) enum drm_map_flags flags; /**< Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) void *handle; /**< User-space: "Handle" to pass to mmap() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /**< Kernel-space: kernel-virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int mtrr; /**< MTRR slot used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * DRM_IOCTL_GET_CLIENT ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct drm_client {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int idx; /**< Which client desired? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int auth; /**< Is client authenticated? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long pid; /**< Process ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long uid; /**< User ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long magic; /**< Magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long iocs; /**< Ioctl count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) enum drm_stat_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) _DRM_STAT_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) _DRM_STAT_OPENS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) _DRM_STAT_CLOSES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) _DRM_STAT_IOCTLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) _DRM_STAT_LOCKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) _DRM_STAT_UNLOCKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) _DRM_STAT_VALUE, /**< Generic value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) _DRM_STAT_IRQ, /**< IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) _DRM_STAT_DMA, /**< DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) _DRM_STAT_MISSED /**< Missed DMA opportunity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Add to the *END* of the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * DRM_IOCTL_GET_STATS ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct drm_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) enum drm_stat_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } data[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Hardware locking flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) enum drm_lock_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* These *HALT* flags aren't supported yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) -- they will be used to support the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) full-screen DGA-like mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * \sa drmGetLock() and drmUnlock().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct drm_lock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) enum drm_lock_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * DMA flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * \warning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * These values \e must match xf86drm.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * \sa drm_dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) enum drm_dma_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Flags for DMA buffer dispatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) _DRM_DMA_BLOCK = 0x01, /**<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Block until buffer dispatched.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * \note The buffer may not yet have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * been processed by the hardware --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * getting a hardware lock with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * hardware quiescent will ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * that the buffer has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Flags for DMA buffer request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * \sa drmAddBufs().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct drm_buf_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int count; /**< Number of buffers of this size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int size; /**< Size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int low_mark; /**< Low water mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int high_mark; /**< High water mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long agp_start; /**<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Start address of where the AGP buffers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * in the AGP aperture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * DRM_IOCTL_INFO_BUFS ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct drm_buf_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int count; /**< Entries in list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct drm_buf_desc __user *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * DRM_IOCTL_FREE_BUFS ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct drm_buf_free {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int __user *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Buffer information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * \sa drm_buf_map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct drm_buf_pub {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int idx; /**< Index into the master buffer list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int total; /**< Buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int used; /**< Amount of buffer in use (for DMA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) void __user *address; /**< Address of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * DRM_IOCTL_MAP_BUFS ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct drm_buf_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int count; /**< Length of the buffer list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #ifdef __cplusplus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) void __user *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) void __user *virtual; /**< Mmap'd area in user-virtual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct drm_buf_pub __user *list; /**< Buffer information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * DRM_IOCTL_DMA ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Indices here refer to the offset into the buffer list in drm_buf_get.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * \sa drmDMA().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct drm_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int context; /**< Context handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int send_count; /**< Number of buffers to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int __user *send_indices; /**< List of handles to buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int __user *send_sizes; /**< Lengths of data to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enum drm_dma_flags flags; /**< Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int request_count; /**< Number of buffers requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int request_size; /**< Desired size for buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int __user *request_indices; /**< Buffer information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int __user *request_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int granted_count; /**< Number of buffers granted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) enum drm_ctx_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) _DRM_CONTEXT_PRESERVED = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) _DRM_CONTEXT_2DONLY = 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * DRM_IOCTL_ADD_CTX ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * \sa drmCreateContext() and drmDestroyContext().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct drm_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) drm_context_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) enum drm_ctx_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * DRM_IOCTL_RES_CTX ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct drm_ctx_res {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct drm_ctx __user *contexts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct drm_draw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) drm_drawable_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) DRM_DRAWABLE_CLIPRECTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) } drm_drawable_info_type_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct drm_update_draw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) drm_drawable_t handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned long long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct drm_auth {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) drm_magic_t magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * DRM_IOCTL_IRQ_BUSID ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * \sa drmGetInterruptFromBusID().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct drm_irq_busid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int irq; /**< IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int busnum; /**< bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int devnum; /**< device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int funcnum; /**< function number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) enum drm_vblank_seq_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* bits 1-6 are reserved for high crtcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct drm_wait_vblank_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) enum drm_vblank_seq_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned long signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct drm_wait_vblank_reply {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) enum drm_vblank_seq_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned int sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) long tval_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) long tval_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * \sa drmWaitVBlank().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) union drm_wait_vblank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct drm_wait_vblank_request request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct drm_wait_vblank_reply reply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define _DRM_PRE_MODESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define _DRM_POST_MODESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * DRM_IOCTL_MODESET_CTL ioctl argument type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * \sa drmModesetCtl().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct drm_modeset_ctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) __u32 crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) __u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * DRM_IOCTL_AGP_ENABLE ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * \sa drmAgpEnable().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct drm_agp_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned long mode; /**< AGP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * \sa drmAgpAlloc() and drmAgpFree().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct drm_agp_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned long size; /**< In bytes -- will round to page boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned long handle; /**< Used for binding / unbinding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned long type; /**< Type of memory to allocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned long physical; /**< Physical used by i810 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * \sa drmAgpBind() and drmAgpUnbind().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct drm_agp_binding {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) unsigned long handle; /**< From drm_agp_buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned long offset; /**< In bytes -- will round to page boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * DRM_IOCTL_AGP_INFO ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * drmAgpVendorId() and drmAgpDeviceId().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct drm_agp_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int agp_version_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int agp_version_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned long mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned long aperture_base; /* physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned long aperture_size; /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned long memory_allowed; /* bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned long memory_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* PCI information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned short id_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned short id_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * DRM_IOCTL_SG_ALLOC ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct drm_scatter_gather {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned long size; /**< In bytes -- will round to page boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned long handle; /**< Used for mapping / unmapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * DRM_IOCTL_SET_VERSION ioctl argument type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct drm_set_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int drm_di_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int drm_di_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int drm_dd_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int drm_dd_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /** DRM_IOCTL_GEM_CLOSE ioctl argument type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct drm_gem_close {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /** Handle of the object to be closed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /** DRM_IOCTL_GEM_FLINK ioctl argument type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct drm_gem_flink {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /** Handle for the object being named */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /** Returned global name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) __u32 name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /** DRM_IOCTL_GEM_OPEN ioctl argument type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct drm_gem_open {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /** Name of object being opened */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) __u32 name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /** Returned handle for the object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /** Returned size of the object */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define DRM_CAP_DUMB_BUFFER 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define DRM_CAP_VBLANK_HIGH_CRTC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define DRM_CAP_DUMB_PREFER_SHADOW 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define DRM_CAP_PRIME 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define DRM_PRIME_CAP_IMPORT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define DRM_PRIME_CAP_EXPORT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define DRM_CAP_ASYNC_PAGE_FLIP 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * combination for the hardware cursor. The intention is that a hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * agnostic userspace can query a cursor plane size to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * Note that the cross-driver contract is to merely return a valid size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * drivers are free to attach another meaning on top, eg. i915 returns the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * maximum plane size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define DRM_CAP_CURSOR_WIDTH 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define DRM_CAP_CURSOR_HEIGHT 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define DRM_CAP_ADDFB2_MODIFIERS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define DRM_CAP_PAGE_FLIP_TARGET 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define DRM_CAP_SYNCOBJ 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define DRM_CAP_SYNCOBJ_TIMELINE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /** DRM_IOCTL_GET_CAP ioctl argument type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct drm_get_cap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) __u64 capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) __u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * DRM_CLIENT_CAP_STEREO_3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * if set to 1, the DRM core will expose the stereo 3D capabilities of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * monitor by advertising the supported 3D layouts in the flags of struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * drm_mode_modeinfo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define DRM_CLIENT_CAP_STEREO_3D 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * DRM_CLIENT_CAP_UNIVERSAL_PLANES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * If set to 1, the DRM core will expose all planes (overlay, primary, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * cursor) to userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * DRM_CLIENT_CAP_ATOMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * If set to 1, the DRM core will expose atomic properties to userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define DRM_CLIENT_CAP_ATOMIC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * DRM_CLIENT_CAP_ASPECT_RATIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * If set to 1, the DRM core will provide aspect ratio information in modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define DRM_CLIENT_CAP_ASPECT_RATIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * If set to 1, the DRM core will expose special connectors to be used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * writing back to memory the scene setup in the commit. Depends on client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * also supporting DRM_CLIENT_CAP_ATOMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct drm_set_client_cap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) __u64 capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) __u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define DRM_RDWR O_RDWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define DRM_CLOEXEC O_CLOEXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct drm_prime_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /** Flags.. only applicable for handle->fd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /** Returned dmabuf file descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) __s32 fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct drm_syncobj_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct drm_syncobj_destroy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct drm_syncobj_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) __s32 fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct drm_syncobj_transfer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) __u32 src_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) __u32 dst_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) __u64 src_point;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) __u64 dst_point;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct drm_syncobj_wait {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) __u64 handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* absolute timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) __s64 timeout_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) __u32 count_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) __u32 first_signaled; /* only valid when not waiting all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct drm_syncobj_timeline_wait {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __u64 handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* wait on specific timeline point for every handles*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) __u64 points;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* absolute timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) __s64 timeout_nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __u32 count_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) __u32 first_signaled; /* only valid when not waiting all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct drm_syncobj_array {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) __u64 handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) __u32 count_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct drm_syncobj_timeline_array {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) __u64 handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) __u64 points;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) __u32 count_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* Query current scanout sequence number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct drm_crtc_get_sequence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) __u32 crtc_id; /* requested crtc_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) __u32 active; /* return: crtc output is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) __u64 sequence; /* return: most recent vblank sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) __s64 sequence_ns; /* return: most recent time of first pixel out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Queue event to be delivered at specified sequence. Time stamp marks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * when the first pixel of the refresh cycle leaves the display engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * for the display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct drm_crtc_queue_sequence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) __u32 crtc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) __u64 sequence; /* on input, target sequence. on output, actual sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) __u64 user_data; /* user data passed to event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #include "drm_mode.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define DRM_IOCTL_BASE 'd'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * Device specific ioctls should only be in their respective headers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * The device specific ioctl range is from 0x40 to 0x9f.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * Generic IOCTLS restart at 0xA0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * drmCommandReadWrite().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define DRM_COMMAND_BASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define DRM_COMMAND_END 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * Header for events written back to userspace on the drm fd. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * type defines the type of event, the length specifies the total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * length of the event (including the header), and user_data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * typically a 64 bit value passed with the ioctl that triggered the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * event. A read on the drm fd will always only return complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * events, that is, if for example the read buffer is 100 bytes, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * there are two 64 byte events pending, only one will be returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * up are chipset specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct drm_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) __u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) __u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define DRM_EVENT_VBLANK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define DRM_EVENT_FLIP_COMPLETE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define DRM_EVENT_CRTC_SEQUENCE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct drm_event_vblank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct drm_event base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) __u64 user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) __u32 tv_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) __u32 tv_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) __u32 sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) __u32 crtc_id; /* 0 on older kernels that do not support this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* Event delivered at sequence. Time stamp marks when the first pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * of the refresh cycle leaves the display engine for the display
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct drm_event_crtc_sequence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct drm_event base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) __u64 user_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) __s64 time_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) __u64 sequence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* typedef area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #ifndef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) typedef struct drm_clip_rect drm_clip_rect_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) typedef struct drm_drawable_info drm_drawable_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) typedef struct drm_tex_region drm_tex_region_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) typedef struct drm_hw_lock drm_hw_lock_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) typedef struct drm_version drm_version_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) typedef struct drm_unique drm_unique_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) typedef struct drm_list drm_list_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) typedef struct drm_block drm_block_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) typedef struct drm_control drm_control_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) typedef enum drm_map_type drm_map_type_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) typedef enum drm_map_flags drm_map_flags_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) typedef struct drm_map drm_map_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) typedef struct drm_client drm_client_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) typedef enum drm_stat_type drm_stat_type_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) typedef struct drm_stats drm_stats_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) typedef enum drm_lock_flags drm_lock_flags_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) typedef struct drm_lock drm_lock_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) typedef enum drm_dma_flags drm_dma_flags_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) typedef struct drm_buf_desc drm_buf_desc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) typedef struct drm_buf_info drm_buf_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) typedef struct drm_buf_free drm_buf_free_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) typedef struct drm_buf_pub drm_buf_pub_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) typedef struct drm_buf_map drm_buf_map_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) typedef struct drm_dma drm_dma_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) typedef union drm_wait_vblank drm_wait_vblank_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) typedef struct drm_agp_mode drm_agp_mode_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) typedef enum drm_ctx_flags drm_ctx_flags_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) typedef struct drm_ctx drm_ctx_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) typedef struct drm_ctx_res drm_ctx_res_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) typedef struct drm_draw drm_draw_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) typedef struct drm_update_draw drm_update_draw_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) typedef struct drm_auth drm_auth_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) typedef struct drm_irq_busid drm_irq_busid_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) typedef struct drm_agp_buffer drm_agp_buffer_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) typedef struct drm_agp_binding drm_agp_binding_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) typedef struct drm_agp_info drm_agp_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) typedef struct drm_scatter_gather drm_scatter_gather_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) typedef struct drm_set_version drm_set_version_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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