^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2014 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Permission is hereby granted, free of charge, to any person obtaining a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * copy of this software and associated documentation files (the "Software"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * to deal in the Software without restriction, including without limitation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the rights to use, copy, modify, merge, publish, distribute, sublicense,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * and/or sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Software is furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Kevin E. Martin <martin@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Gareth Hughes <gareth@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Keith Whitwell <keith@tungstengraphics.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef __AMDGPU_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define __AMDGPU_DRM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "drm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern "C" {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRM_AMDGPU_GEM_CREATE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRM_AMDGPU_GEM_MMAP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRM_AMDGPU_CTX 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRM_AMDGPU_BO_LIST 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRM_AMDGPU_CS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRM_AMDGPU_INFO 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRM_AMDGPU_GEM_METADATA 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DRM_AMDGPU_GEM_VA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DRM_AMDGPU_WAIT_CS 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DRM_AMDGPU_GEM_OP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DRM_AMDGPU_GEM_USERPTR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DRM_AMDGPU_WAIT_FENCES 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DRM_AMDGPU_VM 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DRM_AMDGPU_SCHED 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * DOC: memory domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Memory in this pool could be swapped out to disk if there is pressure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * pages of system memory, allows GPU access system memory in a linezrized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * fashion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * carved out by the BIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * across shader threads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * execution of all the waves on a device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * for appending data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AMDGPU_GEM_DOMAIN_CPU 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AMDGPU_GEM_DOMAIN_GTT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AMDGPU_GEM_DOMAIN_VRAM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AMDGPU_GEM_DOMAIN_GDS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AMDGPU_GEM_DOMAIN_GWS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AMDGPU_GEM_DOMAIN_OA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) AMDGPU_GEM_DOMAIN_GTT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) AMDGPU_GEM_DOMAIN_VRAM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) AMDGPU_GEM_DOMAIN_GDS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) AMDGPU_GEM_DOMAIN_GWS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) AMDGPU_GEM_DOMAIN_OA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Flag that CPU access will be required for the case of VRAM domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Flag that CPU access will not work, this VRAM domain is invisible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Flag that USWC attributes should be used for GTT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Flag that the memory should be in VRAM and cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Flag that create shadow bo(GTT) while allocating vram bo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Flag that allocating the BO should use linear VRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Flag that BO is always valid in this VM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Flag that BO sharing will be explicitly synchronized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Flag that indicates allocating MQD gart on GFX9, where the mtype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * for the second page onward should be set to NC. It should never
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * be used by user space applications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Flag that BO may contain sensitive data that must be wiped before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * releasing the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Flag that BO will be encrypted and that the TMZ bit should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * set in the PTEs when mapping this buffer via GPUVM or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * accessing it with various hw blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct drm_amdgpu_gem_create_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /** the requested memory size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __u64 bo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /** physical start_addr alignment in bytes for some HW requirements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __u64 alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /** the requested memory domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __u64 domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /** allocation flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __u64 domain_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct drm_amdgpu_gem_create_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /** returned GEM object handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) union drm_amdgpu_gem_create {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct drm_amdgpu_gem_create_in in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct drm_amdgpu_gem_create_out out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /** Opcode to create new residency list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AMDGPU_BO_LIST_OP_CREATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /** Opcode to destroy previously created residency list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AMDGPU_BO_LIST_OP_DESTROY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /** Opcode to update resource information in the list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AMDGPU_BO_LIST_OP_UPDATE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct drm_amdgpu_bo_list_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /** Type of operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) __u32 operation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /** Handle of list or 0 if we want to create one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __u32 list_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /** Number of BOs in list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) __u32 bo_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /** Size of each element describing BO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __u32 bo_info_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /** Pointer to array describing BOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __u64 bo_info_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct drm_amdgpu_bo_list_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /** Handle of BO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __u32 bo_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /** New (if specified) BO priority to be used during migration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) __u32 bo_priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct drm_amdgpu_bo_list_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /** Handle of resource list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __u32 list_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) union drm_amdgpu_bo_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct drm_amdgpu_bo_list_in in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct drm_amdgpu_bo_list_out out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* context related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AMDGPU_CTX_OP_ALLOC_CTX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AMDGPU_CTX_OP_FREE_CTX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AMDGPU_CTX_OP_QUERY_STATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AMDGPU_CTX_OP_QUERY_STATE2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* GPU reset status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AMDGPU_CTX_NO_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* this the context caused it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AMDGPU_CTX_GUILTY_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* some other context caused it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AMDGPU_CTX_INNOCENT_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* unknown cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AMDGPU_CTX_UNKNOWN_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* indicate gpu reset occured after ctx created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* indicate vram lost occured after ctx created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* indicate some job from this context once cause gpu hang */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* indicate some errors are detected by RAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Context priority level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AMDGPU_CTX_PRIORITY_UNSET -2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AMDGPU_CTX_PRIORITY_LOW -512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define AMDGPU_CTX_PRIORITY_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * CAP_SYS_NICE or DRM_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AMDGPU_CTX_PRIORITY_HIGH 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct drm_amdgpu_ctx_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /** AMDGPU_CTX_OP_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) __u32 op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /** For future use, no flags defined so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) __u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /** AMDGPU_CTX_PRIORITY_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __s32 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) union drm_amdgpu_ctx_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) __u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /** For future use, no flags defined so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /** Number of resets caused by this context so far. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __u32 hangs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /** Reset status since the last call of the ioctl. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __u32 reset_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) union drm_amdgpu_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct drm_amdgpu_ctx_in in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) union drm_amdgpu_ctx_out out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* vm ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define AMDGPU_VM_OP_RESERVE_VMID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define AMDGPU_VM_OP_UNRESERVE_VMID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct drm_amdgpu_vm_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /** AMDGPU_VM_OP_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __u32 op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct drm_amdgpu_vm_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /** For future use, no flags defined so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) union drm_amdgpu_vm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct drm_amdgpu_vm_in in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct drm_amdgpu_vm_out out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* sched ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct drm_amdgpu_sched_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* AMDGPU_SCHED_OP_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __u32 op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) __u32 fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /** AMDGPU_CTX_PRIORITY_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) __s32 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) __u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) union drm_amdgpu_sched {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct drm_amdgpu_sched_in in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * This is not a reliable API and you should expect it to fail for any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * number of reasons and have fallback path that do not use userptr to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * perform any operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct drm_amdgpu_gem_userptr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) __u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* AMDGPU_GEM_USERPTR_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Resulting GEM handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* SI-CI-VI: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* GFX9 and later: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define AMDGPU_TILING_SCANOUT_SHIFT 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define AMDGPU_TILING_SCANOUT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Set/Get helpers for tiling flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define AMDGPU_TILING_SET(field, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define AMDGPU_TILING_GET(value, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /** The same structure is shared for input/output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct drm_amdgpu_gem_metadata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /** GEM Object handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /** Do we want get or set metadata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) __u32 op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /** For future use, no flags defined so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) __u64 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /** family specific tiling info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) __u64 tiling_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) __u32 data_size_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __u32 data[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) } data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct drm_amdgpu_gem_mmap_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /** the GEM object handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct drm_amdgpu_gem_mmap_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /** mmap offset from the vma offset manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __u64 addr_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) union drm_amdgpu_gem_mmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct drm_amdgpu_gem_mmap_in in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct drm_amdgpu_gem_mmap_out out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct drm_amdgpu_gem_wait_idle_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /** GEM object handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /** For future use, no flags defined so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /** Absolute timeout to wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) __u64 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct drm_amdgpu_gem_wait_idle_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /** BO status: 0 - BO is idle, 1 - BO is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) __u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /** Returned current memory domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __u32 domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) union drm_amdgpu_gem_wait_idle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct drm_amdgpu_gem_wait_idle_in in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct drm_amdgpu_gem_wait_idle_out out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct drm_amdgpu_wait_cs_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Command submission handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * handle equals 0 means none to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * handle equals ~0ull means wait for the latest sequence number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) __u64 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /** Absolute timeout to wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) __u64 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) __u32 ip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) __u32 ip_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) __u32 ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) __u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct drm_amdgpu_wait_cs_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /** CS status: 0 - CS completed, 1 - CS still busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) __u64 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) union drm_amdgpu_wait_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct drm_amdgpu_wait_cs_in in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct drm_amdgpu_wait_cs_out out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct drm_amdgpu_fence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) __u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) __u32 ip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) __u32 ip_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) __u32 ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) __u64 seq_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct drm_amdgpu_wait_fences_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /** This points to uint64_t * which points to fences */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) __u64 fences;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __u32 fence_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) __u32 wait_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __u64 timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct drm_amdgpu_wait_fences_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) __u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) __u32 first_signaled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) union drm_amdgpu_wait_fences {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct drm_amdgpu_wait_fences_in in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct drm_amdgpu_wait_fences_out out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define AMDGPU_GEM_OP_SET_PLACEMENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Sets or returns a value associated with a buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct drm_amdgpu_gem_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /** GEM object handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /** AMDGPU_GEM_OP_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) __u32 op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /** Input or return value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) __u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define AMDGPU_VA_OP_MAP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define AMDGPU_VA_OP_UNMAP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define AMDGPU_VA_OP_CLEAR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define AMDGPU_VA_OP_REPLACE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Delay the page table update till the next CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Mapping flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* readable mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define AMDGPU_VM_PAGE_READABLE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* writable mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* executable mapping, new for VI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* partially resident texture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define AMDGPU_VM_PAGE_PRT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* MTYPE flags use bit 5 to 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define AMDGPU_VM_MTYPE_MASK (0xf << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Use Non Coherent MTYPE instead of default MTYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define AMDGPU_VM_MTYPE_NC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Use Write Combine MTYPE instead of default MTYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define AMDGPU_VM_MTYPE_WC (2 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Use Cache Coherent MTYPE instead of default MTYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define AMDGPU_VM_MTYPE_CC (3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Use UnCached MTYPE instead of default MTYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define AMDGPU_VM_MTYPE_UC (4 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Use Read Write MTYPE instead of default MTYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define AMDGPU_VM_MTYPE_RW (5 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct drm_amdgpu_gem_va {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /** GEM object handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /** AMDGPU_VA_OP_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) __u32 operation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /** AMDGPU_VM_PAGE_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /** va address to assign . Must be correctly aligned.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) __u64 va_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /** Specify offset inside of BO to assign. Must be correctly aligned.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) __u64 offset_in_bo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /** Specify mapping size. Must be correctly aligned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) __u64 map_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define AMDGPU_HW_IP_GFX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define AMDGPU_HW_IP_COMPUTE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define AMDGPU_HW_IP_DMA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define AMDGPU_HW_IP_UVD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define AMDGPU_HW_IP_VCE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define AMDGPU_HW_IP_UVD_ENC 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define AMDGPU_HW_IP_VCN_DEC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define AMDGPU_HW_IP_VCN_ENC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define AMDGPU_HW_IP_VCN_JPEG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define AMDGPU_HW_IP_NUM 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define AMDGPU_CHUNK_ID_IB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define AMDGPU_CHUNK_ID_FENCE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct drm_amdgpu_cs_chunk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) __u32 chunk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) __u32 length_dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) __u64 chunk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct drm_amdgpu_cs_in {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /** Rendering context id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) __u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /** Handle of resource list associated with CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) __u32 bo_list_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) __u32 num_chunks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /** this points to __u64 * which point to cs chunks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) __u64 chunks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct drm_amdgpu_cs_out {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __u64 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) union drm_amdgpu_cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct drm_amdgpu_cs_in in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct drm_amdgpu_cs_out out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Specify flags to be used for IB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* This IB should be submitted to CE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define AMDGPU_IB_FLAG_CE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Preamble flag, which means the IB could be dropped if no context switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* The IB fence should do the L2 writeback but not invalidate any shader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * caches (L2/vL1/sL1/I$). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * This will reset wave ID counters for the IB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Flag the IB as secure (TMZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define AMDGPU_IB_FLAGS_SECURE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Tell KMD to flush and invalidate caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct drm_amdgpu_cs_chunk_ib {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /** AMDGPU_IB_FLAG_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /** Virtual address to begin IB execution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) __u64 va_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /** Size of submission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) __u32 ib_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /** HW IP to submit to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) __u32 ip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /** HW IP index of the same type to submit to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) __u32 ip_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /** Ring index to submit to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) __u32 ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct drm_amdgpu_cs_chunk_dep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __u32 ip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) __u32 ip_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) __u32 ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) __u32 ctx_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) __u64 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct drm_amdgpu_cs_chunk_fence {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) __u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct drm_amdgpu_cs_chunk_sem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct drm_amdgpu_cs_chunk_syncobj {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) __u64 point;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) union drm_amdgpu_fence_to_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct drm_amdgpu_fence fence;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) __u32 what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) } in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) __u32 handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) } out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct drm_amdgpu_cs_chunk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct drm_amdgpu_cs_chunk_ib ib_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct drm_amdgpu_cs_chunk_fence fence_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define AMDGPU_IDS_FLAGS_FUSION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define AMDGPU_IDS_FLAGS_TMZ 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* indicate if acceleration can be working */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define AMDGPU_INFO_ACCEL_WORKING 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* get the crtc_id from the mode object id? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define AMDGPU_INFO_CRTC_FROM_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* query hw IP info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define AMDGPU_INFO_HW_IP_INFO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* query hw IP instance count for the specified type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define AMDGPU_INFO_HW_IP_COUNT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* timestamp for GL_ARB_timer_query */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define AMDGPU_INFO_TIMESTAMP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Query the firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define AMDGPU_INFO_FW_VERSION 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Subquery id: Query VCE firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define AMDGPU_INFO_FW_VCE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Subquery id: Query UVD firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define AMDGPU_INFO_FW_UVD 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Subquery id: Query GMC firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define AMDGPU_INFO_FW_GMC 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Subquery id: Query GFX ME firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define AMDGPU_INFO_FW_GFX_ME 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Subquery id: Query GFX PFP firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define AMDGPU_INFO_FW_GFX_PFP 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Subquery id: Query GFX CE firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define AMDGPU_INFO_FW_GFX_CE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Subquery id: Query GFX RLC firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define AMDGPU_INFO_FW_GFX_RLC 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Subquery id: Query GFX MEC firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define AMDGPU_INFO_FW_GFX_MEC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Subquery id: Query SMC firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define AMDGPU_INFO_FW_SMC 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* Subquery id: Query SDMA firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define AMDGPU_INFO_FW_SDMA 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Subquery id: Query PSP SOS firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define AMDGPU_INFO_FW_SOS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* Subquery id: Query PSP ASD firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define AMDGPU_INFO_FW_ASD 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Subquery id: Query VCN firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define AMDGPU_INFO_FW_VCN 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Subquery id: Query GFX RLC SRLC firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Subquery id: Query GFX RLC SRLG firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Subquery id: Query GFX RLC SRLS firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* Subquery id: Query DMCU firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define AMDGPU_INFO_FW_DMCU 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define AMDGPU_INFO_FW_TA 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Subquery id: Query DMCUB firmware version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define AMDGPU_INFO_FW_DMCUB 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* number of bytes moved for TTM migration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* the used VRAM size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define AMDGPU_INFO_VRAM_USAGE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* the used GTT size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define AMDGPU_INFO_GTT_USAGE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Information about GDS, etc. resource configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define AMDGPU_INFO_GDS_CONFIG 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Query information about VRAM and GTT domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define AMDGPU_INFO_VRAM_GTT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Query information about register in MMR address space*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define AMDGPU_INFO_READ_MMR_REG 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /* Query information about device: rev id, family, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define AMDGPU_INFO_DEV_INFO 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* visible vram usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* number of TTM buffer evictions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define AMDGPU_INFO_NUM_EVICTIONS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Query memory about VRAM and GTT domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define AMDGPU_INFO_MEMORY 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Query vce clock table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Query vbios related information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define AMDGPU_INFO_VBIOS 0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* Subquery id: Query vbios size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define AMDGPU_INFO_VBIOS_SIZE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Subquery id: Query vbios image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define AMDGPU_INFO_VBIOS_IMAGE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Query UVD handles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define AMDGPU_INFO_NUM_HANDLES 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Query sensor related information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define AMDGPU_INFO_SENSOR 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Subquery id: Query GPU shader clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* Subquery id: Query GPU memory clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Subquery id: Query GPU temperature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* Subquery id: Query GPU load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Subquery id: Query average GPU power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Subquery id: Query northbridge voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define AMDGPU_INFO_SENSOR_VDDNB 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Subquery id: Query graphics voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Subquery id: Query GPU stable pstate shader clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Subquery id: Query GPU stable pstate memory clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Number of VRAM page faults on CPU access. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* query ras mask of enabled features*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* RAS MASK: UMC (VRAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* RAS MASK: SDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* RAS MASK: GFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* RAS MASK: MMHUB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* RAS MASK: ATHUB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* RAS MASK: PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* RAS MASK: HDP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* RAS MASK: XGMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* RAS MASK: DF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* RAS MASK: SMN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* RAS MASK: SEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* RAS MASK: MP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* RAS MASK: MP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* RAS MASK: FUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct drm_amdgpu_query_fw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /** AMDGPU_INFO_FW_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) __u32 fw_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * Index of the IP if there are more IPs of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * the same type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) __u32 ip_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * Index of the engine. Whether this is used depends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * on the firmware type. (e.g. MEC, SDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) __u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Input structure for the INFO ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct drm_amdgpu_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Where the return value will be stored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) __u64 return_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* The size of the return value. Just like "size" in "snprintf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * it limits how many bytes the kernel can write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) __u32 return_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* The query request id. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) __u32 query;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) __u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) } mode_crtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /** AMDGPU_HW_IP_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) __u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * Index of the IP if there are more IPs of the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) __u32 ip_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) } query_hw_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) __u32 dword_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /** number of registers to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) __u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) __u32 instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /** For future use, no flags defined so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) __u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) } read_mmr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct drm_amdgpu_query_fw query_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) __u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) __u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) } vbios_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) } sensor_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct drm_amdgpu_info_gds {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /** GDS GFX partition size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) __u32 gds_gfx_partition_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /** GDS compute partition size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) __u32 compute_partition_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /** total GDS memory size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) __u32 gds_total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /** GWS size per GFX partition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) __u32 gws_per_gfx_partition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /** GSW size per compute partition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) __u32 gws_per_compute_partition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /** OA size per GFX partition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) __u32 oa_per_gfx_partition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /** OA size per compute partition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) __u32 oa_per_compute_partition;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct drm_amdgpu_info_vram_gtt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) __u64 vram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) __u64 vram_cpu_accessible_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) __u64 gtt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct drm_amdgpu_heap_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /** max. physical memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) __u64 total_heap_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /** Theoretical max. available memory in the given heap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) __u64 usable_heap_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * Number of bytes allocated in the heap. This includes all processes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * and private allocations in the kernel. It changes when new buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * are allocated, freed, and moved. It cannot be larger than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * heap_size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) __u64 heap_usage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * Theoretical possible max. size of buffer which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * could be allocated in the given heap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) __u64 max_allocation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct drm_amdgpu_memory_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct drm_amdgpu_heap_info vram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct drm_amdgpu_heap_info cpu_accessible_vram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct drm_amdgpu_heap_info gtt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct drm_amdgpu_info_firmware {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) __u32 ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) __u32 feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define AMDGPU_VRAM_TYPE_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define AMDGPU_VRAM_TYPE_GDDR1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define AMDGPU_VRAM_TYPE_DDR2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define AMDGPU_VRAM_TYPE_GDDR3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define AMDGPU_VRAM_TYPE_GDDR4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define AMDGPU_VRAM_TYPE_GDDR5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define AMDGPU_VRAM_TYPE_HBM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define AMDGPU_VRAM_TYPE_DDR3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define AMDGPU_VRAM_TYPE_DDR4 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define AMDGPU_VRAM_TYPE_GDDR6 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct drm_amdgpu_info_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /** PCI Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) __u32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /** Internal chip revision: A0, A1, etc.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) __u32 chip_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) __u32 external_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /** Revision id in PCI Config space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) __u32 pci_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) __u32 family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) __u32 num_shader_engines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) __u32 num_shader_arrays_per_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) __u32 gpu_counter_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) __u64 max_engine_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) __u64 max_memory_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* cu information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) __u32 cu_active_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* NOTE: cu_ao_mask is INVALID, DON'T use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) __u32 cu_ao_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) __u32 cu_bitmap[4][4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /** Render backend pipe mask. One render backend is CB+DB. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) __u32 enabled_rb_pipes_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) __u32 num_rb_pipes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) __u32 num_hw_gfx_contexts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) __u64 ids_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /** Starting virtual address for UMDs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) __u64 virtual_address_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /** The maximum virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) __u64 virtual_address_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /** Required alignment of virtual addresses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) __u32 virtual_address_alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /** Page table entry - fragment size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) __u32 pte_fragment_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) __u32 gart_page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /** constant engine ram size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) __u32 ce_ram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /** video memory type info*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) __u32 vram_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /** video memory bit width*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) __u32 vram_bit_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* vce harvesting instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) __u32 vce_harvest_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* gfx double offchip LDS buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) __u32 gc_double_offchip_lds_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* NGG Primitive Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) __u64 prim_buf_gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* NGG Position Buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) __u64 pos_buf_gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* NGG Control Sideband */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) __u64 cntl_sb_buf_gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* NGG Parameter Cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) __u64 param_buf_gpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) __u32 prim_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) __u32 pos_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) __u32 cntl_sb_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) __u32 param_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* wavefront size*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) __u32 wave_front_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* shader visible vgprs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) __u32 num_shader_visible_vgprs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* CU per shader array*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) __u32 num_cu_per_sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* number of tcc blocks*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) __u32 num_tcc_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* gs vgt table depth*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) __u32 gs_vgt_table_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* gs primitive buffer depth*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) __u32 gs_prim_buffer_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* max gs wavefront per vgt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) __u32 max_gs_waves_per_vgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) __u32 _pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* always on cu bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) __u32 cu_ao_bitmap[4][4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /** Starting high virtual address for UMDs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) __u64 high_va_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /** The maximum high virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) __u64 high_va_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* gfx10 pa_sc_tile_steering_override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) __u32 pa_sc_tile_steering_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* disabled TCCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) __u64 tcc_disabled_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct drm_amdgpu_info_hw_ip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /** Version of h/w IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) __u32 hw_ip_version_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) __u32 hw_ip_version_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /** Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) __u64 capabilities_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /** command buffer address start alignment*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) __u32 ib_start_alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /** command buffer size alignment*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) __u32 ib_size_alignment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /** Bitmask of available rings. Bit 0 means ring 0, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) __u32 available_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) __u32 _pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct drm_amdgpu_info_num_handles {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /** Max handles as supported by firmware for UVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) __u32 uvd_max_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /** Handles currently in use for UVD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) __u32 uvd_used_handles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct drm_amdgpu_info_vce_clock_table_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /** System clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) __u32 sclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /** Memory clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) __u32 mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /** VCE clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) __u32 eclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct drm_amdgpu_info_vce_clock_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) __u32 num_valid_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) __u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * Supported GPU families
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define AMDGPU_FAMILY_UNKNOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define AMDGPU_FAMILY_AI 141 /* Vega10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define AMDGPU_FAMILY_RV 142 /* Raven */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define AMDGPU_FAMILY_NV 143 /* Navi10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #if defined(__cplusplus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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