Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __SOUND_WSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __SOUND_WSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Definitions for CS4231 & InterWave chips & compatible chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <sound/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <sound/cs4231-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* defines for codec.mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define WSS_MODE_NONE	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define WSS_MODE_PLAY	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define WSS_MODE_RECORD	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define WSS_MODE_TIMER	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define WSS_MODE_OPEN	(WSS_MODE_PLAY|WSS_MODE_RECORD|WSS_MODE_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* defines for codec.hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define WSS_HW_DETECT        0x0000	/* let CS4231 driver detect chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define WSS_HW_DETECT3	0x0001	/* allow mode 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define WSS_HW_TYPE_MASK	0xff00	/* type mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define WSS_HW_CS4231_MASK   0x0100	/* CS4231 serie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define WSS_HW_CS4231        0x0100	/* CS4231 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define WSS_HW_CS4231A       0x0101	/* CS4231A chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define WSS_HW_AD1845	0x0102	/* AD1845 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define WSS_HW_CS4232_MASK   0x0200	/* CS4232 serie (has control ports) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define WSS_HW_CS4232        0x0200	/* CS4232 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define WSS_HW_CS4232A       0x0201	/* CS4232A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define WSS_HW_CS4236	0x0202	/* CS4236 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define WSS_HW_CS4236B_MASK	0x0400	/* CS4236B serie (has extended control regs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WSS_HW_CS4235	0x0400	/* CS4235 - Crystal Clear (tm) stereo enhancement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define WSS_HW_CS4236B       0x0401	/* CS4236B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WSS_HW_CS4237B       0x0402	/* CS4237B - SRS 3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WSS_HW_CS4238B	0x0403	/* CS4238B - QSOUND 3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define WSS_HW_CS4239	0x0404	/* CS4239 - Crystal Clear (tm) stereo enhancement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WSS_HW_AD1848_MASK	0x0800	/* AD1848 serie (half duplex) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WSS_HW_AD1847		0x0801	/* AD1847 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WSS_HW_AD1848		0x0802	/* AD1848 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WSS_HW_CS4248		0x0803	/* CS4248 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define WSS_HW_CMI8330		0x0804	/* CMI8330 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WSS_HW_THINKPAD		0x0805	/* Thinkpad 360/750/755 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* compatible, but clones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define WSS_HW_INTERWAVE     0x1000	/* InterWave chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define WSS_HW_OPL3SA2       0x1101	/* OPL3-SA2 chip, similar to cs4231 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define WSS_HW_OPTI93X 	0x1102	/* Opti 930/931/933 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* defines for codec.hwshare */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define WSS_HWSHARE_IRQ	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define WSS_HWSHARE_DMA1	(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define WSS_HWSHARE_DMA2	(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* IBM Thinkpad specific stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AD1848_THINKPAD_CTL_PORT1		0x15e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AD1848_THINKPAD_CTL_PORT2		0x15e9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AD1848_THINKPAD_CS4248_ENABLE_BIT	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct snd_wss {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned long port;		/* base i/o port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct resource *res_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned long cport;		/* control base i/o port (CS4236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct resource *res_cport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	int irq;			/* IRQ line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int dma1;			/* playback DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int dma2;			/* record DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned short version;		/* version of CODEC chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	unsigned short mode;		/* see to WSS_MODE_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	unsigned short hardware;	/* see to WSS_HW_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unsigned short hwshare;		/* shared resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned short single_dma:1,	/* forced single DMA mode (GUS 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 					/* daughter board) or dma1 == dma2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		       ebus_flag:1,	/* SPARC: EBUS present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		       thinkpad_flag:1;	/* Thinkpad CS4248 needs extra help */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct snd_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned char image[32];	/* registers image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	unsigned char eimage[32];	/* extended registers image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned char cimage[16];	/* control registers image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	int mce_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	int calibrate_mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int sw_3d_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unsigned int p_dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned int c_dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct mutex mce_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct mutex open_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	int (*rate_constraint) (struct snd_pcm_runtime *runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	void (*set_playback_format) (struct snd_wss *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 				     struct snd_pcm_hw_params *hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				     unsigned char pdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	void (*set_capture_format) (struct snd_wss *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				    struct snd_pcm_hw_params *hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				    unsigned char cdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	void (*trigger) (struct snd_wss *chip, unsigned int what, int start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	void (*suspend) (struct snd_wss *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	void (*resume) (struct snd_wss *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	void *dma_private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int (*claim_dma) (struct snd_wss *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			  void *dma_private_data, int dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int (*release_dma) (struct snd_wss *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			    void *dma_private_data, int dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* exported functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void snd_cs4236_ext_out(struct snd_wss *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			unsigned char reg, unsigned char val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void snd_wss_mce_up(struct snd_wss *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void snd_wss_mce_down(struct snd_wss *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void snd_wss_overrange(struct snd_wss *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) irqreturn_t snd_wss_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const char *snd_wss_chip_id(struct snd_wss *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int snd_wss_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		      unsigned long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		      unsigned long cport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		      int irq, int dma1, int dma2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		      unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		      unsigned short hwshare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		      struct snd_wss **rchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int snd_wss_pcm(struct snd_wss *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int snd_wss_timer(struct snd_wss *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int snd_wss_mixer(struct snd_wss *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int snd_cs4236_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		      unsigned long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		      unsigned long cport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		      int irq, int dma1, int dma2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		      unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		      unsigned short hwshare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		      struct snd_wss **rchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int snd_cs4236_pcm(struct snd_wss *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int snd_cs4236_mixer(struct snd_wss *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  *  mixer library
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define WSS_SINGLE(xname, xindex, reg, shift, mask, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)   .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)   .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)   .info = snd_wss_info_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)   .get = snd_wss_get_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)   .put = snd_wss_put_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int snd_wss_info_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			struct snd_ctl_elem_info *uinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int snd_wss_get_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			struct snd_ctl_elem_value *ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int snd_wss_put_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			struct snd_ctl_elem_value *ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define WSS_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)   .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)   .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)   .info = snd_wss_info_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)   .get = snd_wss_get_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)   .put = snd_wss_put_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)   .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		   (shift_right << 19) | (mask << 24) | (invert << 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define WSS_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)   .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)   .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)   .info = snd_wss_info_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)   .get = snd_wss_get_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)   .put = snd_wss_put_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)   .tlv = { .p = (xtlv) } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define WSS_DOUBLE_TLV(xname, xindex, left_reg, right_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			shift_left, shift_right, mask, invert, xtlv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)   .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)   .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)   .info = snd_wss_info_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)   .get = snd_wss_get_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)   .put = snd_wss_put_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)   .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		   (shift_right << 19) | (mask << 24) | (invert << 22), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)   .tlv = { .p = (xtlv) } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int snd_wss_info_double(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			struct snd_ctl_elem_info *uinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int snd_wss_get_double(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			struct snd_ctl_elem_value *ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int snd_wss_put_double(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			struct snd_ctl_elem_value *ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif /* __SOUND_WSS_H */