^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Platform data for WM8904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __MFD_WM8994_PDATA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __MFD_WM8994_PDATA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Used to enable configuration of a GPIO to all zeros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define WM8904_GPIO_NO_CONFIG 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * R6 (0x06) - Mic Bias Control 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WM8904_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define WM8904_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WM8904_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WM8904_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WM8904_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WM8904_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WM8904_MICDET_ENA 0x0002 /* MICDET_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WM8904_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WM8904_MICDET_ENA_SHIFT 1 /* MICDET_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WM8904_MICDET_ENA_WIDTH 1 /* MICDET_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WM8904_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WM8904_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WM8904_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define WM8904_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * R7 (0x07) - Mic Bias Control 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define WM8904_MIC_DET_FILTER_ENA 0x8000 /* MIC_DET_FILTER_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WM8904_MIC_DET_FILTER_ENA_MASK 0x8000 /* MIC_DET_FILTER_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WM8904_MIC_DET_FILTER_ENA_SHIFT 15 /* MIC_DET_FILTER_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WM8904_MIC_DET_FILTER_ENA_WIDTH 1 /* MIC_DET_FILTER_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WM8904_MIC_SHORT_FILTER_ENA 0x4000 /* MIC_SHORT_FILTER_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WM8904_MIC_SHORT_FILTER_ENA_MASK 0x4000 /* MIC_SHORT_FILTER_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WM8904_MIC_SHORT_FILTER_ENA_SHIFT 14 /* MIC_SHORT_FILTER_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WM8904_MIC_SHORT_FILTER_ENA_WIDTH 1 /* MIC_SHORT_FILTER_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WM8904_MICBIAS_SEL_MASK 0x0007 /* MICBIAS_SEL - [2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WM8904_MICBIAS_SEL_SHIFT 0 /* MICBIAS_SEL - [2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WM8904_MICBIAS_SEL_WIDTH 3 /* MICBIAS_SEL - [2:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * R121 (0x79) - GPIO Control 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * R122 (0x7A) - GPIO Control 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * R123 (0x7B) - GPIO Control 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * R124 (0x7C) - GPIO Control 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WM8904_MIC_REGS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WM8904_GPIO_REGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WM8904_DRC_REGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WM8904_EQ_REGS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * DRC configurations are specified with a label and a set of register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * values to write (the enable bits will be ignored). At runtime an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * enumerated control will be presented for each DRC block allowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * the user to choose the configuration to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Configurations may be generated by hand or by using the DRC control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * panel provided by the WISCE - see http://www.wolfsonmicro.com/wisce/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct wm8904_drc_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u16 regs[WM8904_DRC_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * ReTune Mobile configurations are specified with a label, sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * rate and set of values to write (the enable bits will be ignored).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Configurations are expected to be generated using the ReTune Mobile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct wm8904_retune_mobile_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u16 regs[WM8904_EQ_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct wm8904_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int num_drc_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct wm8904_drc_cfg *drc_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int num_retune_mobile_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct wm8904_retune_mobile_cfg *retune_mobile_cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 gpio_cfg[WM8904_GPIO_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 mic_cfg[WM8904_MIC_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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