^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/sound/wm8903.h -- Platform data for WM8903
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2010 Wolfson Microelectronics. PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __LINUX_SND_WM8903_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __LINUX_SND_WM8903_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Used to enable configuration of a GPIO to all zeros; a gpio_cfg value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * zero in platform data means "don't touch this pin".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define WM8903_GPIO_CONFIG_ZERO 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * R6 (0x06) - Mic Bias Control 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [5:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WM8903_MICDET_THR_WIDTH 2 /* MICDET_THR - [5:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * WM8903_GPn_FN values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * See datasheets for list of valid values per pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WM8903_GPn_FN_GPIO_OUTPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define WM8903_GPn_FN_BCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define WM8903_GPn_FN_IRQ_OUTPT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define WM8903_GPn_FN_GPIO_INPUT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define WM8903_GPn_FN_MICBIAS_CURRENT_DETECT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WM8903_GPn_FN_MICBIAS_SHORT_DETECT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WM8903_GPn_FN_FLL_LOCK_OUTPUT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WM8903_GPn_FN_FLL_CLOCK_OUTPUT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * R116 (0x74) - GPIO Control 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WM8903_GP1_DIR 0x0080 /* GP1_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define WM8903_GP1_LVL 0x0010 /* GP1_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define WM8903_GP1_PD 0x0008 /* GP1_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define WM8903_GP1_PU 0x0004 /* GP1_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define WM8903_GP1_DB 0x0001 /* GP1_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * R117 (0x75) - GPIO Control 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define WM8903_GP2_DIR 0x0080 /* GP2_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define WM8903_GP2_LVL 0x0010 /* GP2_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define WM8903_GP2_PD 0x0008 /* GP2_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WM8903_GP2_PU 0x0004 /* GP2_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define WM8903_GP2_DB 0x0001 /* GP2_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * R118 (0x76) - GPIO Control 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define WM8903_GP3_DIR 0x0080 /* GP3_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define WM8903_GP3_LVL 0x0010 /* GP3_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define WM8903_GP3_PD 0x0008 /* GP3_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define WM8903_GP3_PU 0x0004 /* GP3_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define WM8903_GP3_DB 0x0001 /* GP3_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * R119 (0x77) - GPIO Control 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define WM8903_GP4_DIR 0x0080 /* GP4_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define WM8903_GP4_LVL 0x0010 /* GP4_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define WM8903_GP4_PD 0x0008 /* GP4_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define WM8903_GP4_PU 0x0004 /* GP4_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define WM8903_GP4_DB 0x0001 /* GP4_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * R120 (0x78) - GPIO Control 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define WM8903_GP5_DIR 0x0080 /* GP5_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define WM8903_GP5_LVL 0x0010 /* GP5_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define WM8903_GP5_PD 0x0008 /* GP5_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define WM8903_GP5_PU 0x0004 /* GP5_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define WM8903_GP5_DB 0x0001 /* GP5_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define WM8903_NUM_GPIO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct wm8903_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bool irq_active_low; /* Set if IRQ active low, default high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Default register value for R6 (Mic bias), used to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * microphone detection. In conjunction with gpio_cfg this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * can be used to route the microphone status signals out onto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * the GPIOs for use with snd_soc_jack_add_gpios().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u16 micdet_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int micdet_delay; /* Delay after microphone detection (ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 gpio_cfg[WM8903_NUM_GPIO]; /* Default register values for GPIO pin mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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