Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * linux/sound/wm2200.h -- Platform data for WM2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2012 Wolfson Microelectronics. PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __LINUX_SND_WM2200_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __LINUX_SND_WM2200_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define WM2200_GPIO_SET 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define WM2200_MAX_MICBIAS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum wm2200_in_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	WM2200_IN_SE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	WM2200_IN_DIFF = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	WM2200_IN_DMIC = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum wm2200_dmic_sup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	WM2200_DMIC_SUP_MICVDD = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	WM2200_DMIC_SUP_MICBIAS1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	WM2200_DMIC_SUP_MICBIAS2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum wm2200_mbias_lvl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	WM2200_MBIAS_LVL_1V5 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	WM2200_MBIAS_LVL_1V8 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	WM2200_MBIAS_LVL_1V9 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	WM2200_MBIAS_LVL_2V0 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	WM2200_MBIAS_LVL_2V2 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	WM2200_MBIAS_LVL_2V4 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	WM2200_MBIAS_LVL_2V5 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	WM2200_MBIAS_LVL_2V6 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct wm2200_micbias {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	enum wm2200_mbias_lvl mb_lvl;      /** Regulated voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	unsigned int discharge:1;          /** Actively discharge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	unsigned int fast_start:1;         /** Enable aggressive startup ramp rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	unsigned int bypass:1;             /** Use bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct wm2200_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	int reset;      /** GPIO controlling /RESET, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	int ldo_ena;    /** GPIO controlling LODENA, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	int irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	int gpio_defaults[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	enum wm2200_in_mode in_mode[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	enum wm2200_dmic_sup dmic_sup[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	/** MICBIAS configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	struct wm2200_micbias micbias[WM2200_MAX_MICBIAS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif