Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * tlv320aic32x4.h  --  TLV320AIC32X4 Soc Audio driver platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2011 Vista Silicon S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Author: Javier Martin <javier.martin@vista-silicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _AIC32X4_PDATA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _AIC32X4_PDATA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AIC32X4_PWR_MICBIAS_2075_LDOIN		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AIC32X4_PWR_AIC32X4_LDO_ENABLE		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* GPIO API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AIC32X4_MFPX_DEFAULT_VALUE	0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AIC32X4_MFP1_DIN_DISABLED	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AIC32X4_MFP1_DIN_ENABLED	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AIC32X4_MFP1_GPIO_IN		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AIC32X4_MFP2_GPIO_OUT_LOW	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AIC32X4_MFP2_GPIO_OUT_HIGH	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AIC32X4_MFP_GPIO_ENABLED	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AIC32X4_MFP5_GPIO_DISABLED	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AIC32X4_MFP5_GPIO_INPUT		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AIC32X4_MFP5_GPIO_OUTPUT	0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AIC32X4_MFP5_GPIO_OUT_LOW	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AIC32X4_MFP5_GPIO_OUT_HIGH	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct aic32x4_setup_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	unsigned int gpio_func[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct aic32x4_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	struct aic32x4_setup_data *setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	u32 power_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	u32 micpga_routing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	bool swapdacs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	int rstn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif