Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This file is provided under a dual BSD/GPLv2 license.  When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __INCLUDE_SOUND_SOF_XTENSA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __INCLUDE_SOUND_SOF_XTENSA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/sof/header.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * Architecture specific debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Xtensa Firmware Oops data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct sof_ipc_dsp_oops_xtensa {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct sof_ipc_dsp_oops_arch_hdr arch_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct sof_ipc_dsp_oops_plat_hdr plat_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	uint32_t exccause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	uint32_t excvaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	uint32_t ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	uint32_t epc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	uint32_t epc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	uint32_t epc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	uint32_t epc4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	uint32_t epc5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	uint32_t epc6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	uint32_t epc7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	uint32_t eps2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	uint32_t eps3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	uint32_t eps4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	uint32_t eps5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	uint32_t eps6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	uint32_t eps7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	uint32_t depc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	uint32_t intenable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	uint32_t interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	uint32_t sar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	uint32_t debugcause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	uint32_t windowbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	uint32_t windowstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	uint32_t excsave1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	uint32_t ar[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }  __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif