^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/sof/header.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Component
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* types of component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum sof_comp_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) SOF_COMP_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) SOF_COMP_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SOF_COMP_DAI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) SOF_COMP_SG_HOST, /**< scatter gather variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SOF_COMP_SG_DAI, /**< scatter gather variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) SOF_COMP_VOLUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SOF_COMP_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SOF_COMP_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SOF_COMP_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SOF_COMP_SPLITTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SOF_COMP_TONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) SOF_COMP_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) SOF_COMP_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) SOF_COMP_EQ_IIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SOF_COMP_EQ_FIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) SOF_COMP_KEYWORD_DETECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) SOF_COMP_KPB, /* A key phrase buffer component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SOF_COMP_SELECTOR, /**< channel selector component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) SOF_COMP_DEMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SOF_COMP_ASRC, /**< Asynchronous sample rate converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SOF_COMP_DCBLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SOF_COMP_SMART_AMP, /**< smart amplifier component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* keep FILEREAD/FILEWRITE as the last ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SOF_COMP_FILEREAD = 10000, /**< host test based file IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* XRUN action for component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SOF_XRUN_STOP 1 /**< stop stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* create new generic component - SOF_IPC_TPLG_COMP_NEW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct sof_ipc_comp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct sof_ipc_cmd_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) uint32_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum sof_comp_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) uint32_t pipeline_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) uint32_t core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* extended data length, 0 if no extended data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) uint32_t ext_data_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Component Buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * SOF memory capabilities, add new ones at the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SOF_MEM_CAPS_RAM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SOF_MEM_CAPS_ROM (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SOF_MEM_CAPS_EXT (1 << 2) /**< external */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SOF_MEM_CAPS_LP (1 << 3) /**< low power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SOF_MEM_CAPS_HP (1 << 4) /**< high performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SOF_MEM_CAPS_DMA (1 << 5) /**< DMA'able */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SOF_MEM_CAPS_CACHE (1 << 6) /**< cacheable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SOF_MEM_CAPS_EXEC (1 << 7) /**< executable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * overrun will cause ring buffer overwrite, instead of XRUN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SOF_BUF_OVERRUN_PERMITTED BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * underrun will cause readback of 0s, instead of XRUN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SOF_BUF_UNDERRUN_PERMITTED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* the UUID size in bytes, shared between FW and host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SOF_UUID_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct sof_ipc_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct sof_ipc_comp comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) uint32_t size; /**< buffer size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) uint32_t caps; /**< SOF_MEM_CAPS_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uint32_t flags; /**< SOF_BUF_ flags defined above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) uint32_t reserved; /**< reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* generic component config data - must always be after struct sof_ipc_comp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct sof_ipc_comp_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct sof_ipc_cmd_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) uint32_t periods_sink; /**< 0 means variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) uint32_t periods_source;/**< 0 means variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) uint32_t reserved1; /**< reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) uint32_t xrun_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) uint32_t reserved[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* generic host component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct sof_ipc_comp_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct sof_ipc_comp comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct sof_ipc_comp_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) uint32_t direction; /**< SOF_IPC_STREAM_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) uint32_t dmac_config; /**< DMA engine specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* generic DAI component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct sof_ipc_comp_dai {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct sof_ipc_comp comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct sof_ipc_comp_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint32_t direction; /**< SOF_IPC_STREAM_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint32_t dai_index; /**< index of this type dai */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) uint32_t type; /**< DAI type - SOF_DAI_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uint32_t reserved; /**< reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* generic mixer component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct sof_ipc_comp_mixer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct sof_ipc_comp comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct sof_ipc_comp_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* volume ramping types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) enum sof_volume_ramp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SOF_VOLUME_LINEAR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SOF_VOLUME_LOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SOF_VOLUME_LINEAR_ZC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SOF_VOLUME_LOG_ZC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* generic volume component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct sof_ipc_comp_volume {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct sof_ipc_comp comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct sof_ipc_comp_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) uint32_t channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) uint32_t min_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) uint32_t max_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) uint32_t ramp; /**< SOF_VOLUME_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) uint32_t initial_ramp; /**< ramp space in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* generic SRC component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct sof_ipc_comp_src {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct sof_ipc_comp comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct sof_ipc_comp_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* either source or sink rate must be non zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) uint32_t source_rate; /**< source rate or 0 for variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) uint32_t sink_rate; /**< sink rate or 0 for variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) uint32_t rate_mask; /**< SOF_RATE_ supported rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* generic ASRC component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct sof_ipc_comp_asrc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct sof_ipc_comp comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct sof_ipc_comp_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* either source or sink rate must be non zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) uint32_t source_rate; /**< Define fixed source rate or */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /**< use 0 to indicate need to get */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**< the rate from stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) uint32_t sink_rate; /**< Define fixed sink rate or */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /**< use 0 to indicate need to get */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /**< the rate from stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /**< When 1 the ASRC tracks and */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /**< compensates for drift. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) uint32_t operation_mode; /**< push 0, pull 1, In push mode the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /**< ASRC consumes a defined number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /**< of frames at input, with varying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**< number of frames at output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /**< In pull mode the ASRC outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /**< a defined number of frames while */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**< number of input frames varies. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) uint32_t reserved[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* generic MUX component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct sof_ipc_comp_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct sof_ipc_comp comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct sof_ipc_comp_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* generic tone generator component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct sof_ipc_comp_tone {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct sof_ipc_comp comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct sof_ipc_comp_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int32_t sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int32_t frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int32_t amplitude;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int32_t freq_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int32_t ampl_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int32_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int32_t period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int32_t repeats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int32_t ramp_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /** \brief Types of processing components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) enum sof_ipc_process_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SOF_PROCESS_NONE = 0, /**< None */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SOF_PROCESS_EQFIR, /**< Intel FIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SOF_PROCESS_EQIIR, /**< Intel IIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SOF_PROCESS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SOF_PROCESS_DEMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SOF_PROCESS_DCBLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SOF_PROCESS_SMART_AMP, /**< Smart Amplifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* generic "effect", "codec" or proprietary processing component */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct sof_ipc_comp_process {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct sof_ipc_comp comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct sof_ipc_comp_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) uint32_t size; /**< size of bespoke data section in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) uint32_t type; /**< sof_ipc_process_type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) uint32_t reserved[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) uint8_t data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* frees components, buffers and pipelines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct sof_ipc_free {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct sof_ipc_cmd_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) uint32_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct sof_ipc_comp_reply {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct sof_ipc_reply rhdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) uint32_t id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) uint32_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /** \brief Types of pipeline scheduling time domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) enum sof_ipc_pipe_sched_time_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct sof_ipc_pipe_new {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct sof_ipc_cmd_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) uint32_t comp_id; /**< component id for pipeline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) uint32_t pipeline_id; /**< pipeline id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uint32_t sched_id; /**< Scheduling component id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) uint32_t core; /**< core we run on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) uint32_t period; /**< execution period in us*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) uint32_t priority; /**< priority level 0 (low) to 10 (max) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) uint32_t period_mips; /**< worst case instruction count per period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) uint32_t time_domain; /**< scheduling time domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct sof_ipc_pipe_ready {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct sof_ipc_cmd_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) uint32_t comp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct sof_ipc_pipe_free {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct sof_ipc_cmd_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) uint32_t comp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct sof_ipc_pipe_comp_connect {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct sof_ipc_cmd_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) uint32_t source_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) uint32_t sink_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* external events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) enum sof_event_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SOF_EVENT_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SOF_KEYWORD_DETECT_DAPM_EVENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* extended data struct for UUID components */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct sof_ipc_comp_ext {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) uint8_t uuid[SOF_UUID_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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