^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file is provided under a dual BSD/GPLv2 license. When using or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * redistributing this file, you may do so under either license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright(c) 2018 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __INCLUDE_SOUND_SOF_DAI_INTEL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/sof/header.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* ssc1: TINTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* ssc1: PINTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* ssc2: SMTATF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* ssc2: MMRATF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* ssc2: PSPSTWFDFD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* ssc2: PSPSRWFDFD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* ssc1: LBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* here is the possibility to define others aux macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* SSP clocks control settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Macros for clks_control field in sof_ipc_dai_ssp_params struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* mclk 0 disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* mclk 1 disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* mclk keep active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* bclk keep active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* fs keep active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* bclk idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* DMIC max. four controllers for eight microphone channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SOF_DAI_INTEL_DMIC_NUM_CTRL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct sof_ipc_dai_ssp_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct sof_ipc_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) uint16_t reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) uint16_t mclk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) uint32_t mclk_rate; /* mclk frequency in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) uint32_t fsync_rate; /* fsync frequency in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) uint32_t bclk_rate; /* bclk frequency in Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* TDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) uint32_t tdm_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) uint32_t rx_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) uint32_t tx_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) uint32_t sample_valid_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) uint16_t tdm_slot_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) uint16_t reserved2; /* alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) uint32_t mclk_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) uint16_t frame_pulse_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) uint16_t tdm_per_slot_padding_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) uint32_t clks_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) uint32_t quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * will be driven, before sending data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct sof_ipc_dai_hda_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct sof_ipc_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) uint32_t link_dma_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) uint32_t rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) uint32_t channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct sof_ipc_dai_alh_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct sof_ipc_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uint32_t stream_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) uint32_t rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) uint32_t channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) uint32_t reserved[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* This struct is defined per 2ch PDM controller available in the platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Normally it is sufficient to set the used microphone specific enables to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * and keep other parameters as zero. The customizations are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * 1. If a device mixes different microphones types with different polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * and/or the absolute polarity matters the PCM signal from a microphone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * can be inverted with the controls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * 2. If the microphones in a stereo pair do not appear in captured stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * in desired order due to board schematics choises they can be swapped with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * the clk_edge parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * that delays the sampling time of data by half cycles of DMIC source clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * can be tried for improvement. However there is no guarantee for this to fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * data integrity problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct sof_ipc_dai_dmic_pdm_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct sof_ipc_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uint16_t id; /**< PDM controller ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* This struct contains the global settings for all 2ch PDM controllers. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * version number used in configuration data is checked vs. version used by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * device driver src/drivers/dmic.c need to match. It is incremented from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * initial value 1 if updates done for the to driver would alter the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * of the microphone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * parameters need to be set as defined in microphone data sheet. E.g. clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * multi-mode capable and there may be denied mic clock frequencies between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * the modes. In such case set the clock range limits of the desired mode to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * avoid the driver to set clock to an illegal rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * The duty cycle could be set to 48-52% if not known. Generally these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * parameters can be altered within data sheet specified limits to match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * required audio application performance power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * The microphone clock needs to be usually about 50-80 times the used audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * sample rate. With highest sample rates above 48 kHz this can relaxed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * somewhat.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * The parameter wake_up_time describes how long time the microphone needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * for the data line to produce valid output from mic clock start. The driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * will mute the captured audio for the given time. The min_clock_on_time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * parameter is used to prevent too short clock bursts to happen. The driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * will keep the clock active after capture stop if this time is not yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * met. The unit for both is microseconds (us). Exceed of 100 ms will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * treated as an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct sof_ipc_dai_dmic_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct sof_ipc_hdr hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) uint32_t driver_ipc_version; /**< Version (1..N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) uint32_t reserved_1; /**< Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) uint16_t fifo_bits; /**< FIFO word length (16 or 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) uint16_t fifo_bits_b; /**< Deprecated since firmware ABI 3.0.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) uint32_t num_pdm_active; /**< Number of active pdm controllers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**< Range is 1..SOF_DAI_INTEL_DMIC_NUM_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) uint32_t wake_up_time; /**< Time from clock start to data (us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* reserved for future use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) uint32_t reserved[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /**< PDM controllers configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct sof_ipc_dai_dmic_pdm_ctrl pdm[SOF_DAI_INTEL_DMIC_NUM_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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