Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __SOUND_SB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __SOUND_SB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Header file for SoundBlaster cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) enum sb_hw_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	SB_HW_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	SB_HW_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	SB_HW_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	SB_HW_201,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	SB_HW_PRO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	SB_HW_JAZZ16,		/* Media Vision Jazz16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	SB_HW_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	SB_HW_16CSP,		/* SB16 with CSP chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	SB_HW_ALS100,		/* Avance Logic ALS100 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	SB_HW_ALS4000,		/* Avance Logic ALS4000 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	SB_HW_DT019X,		/* Diamond Tech. DT-019X / Avance Logic ALS-007 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	SB_HW_CS5530,		/* Cyrix/NatSemi 5530 VSA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SB_OPEN_PCM			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SB_OPEN_MIDI_INPUT		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SB_OPEN_MIDI_OUTPUT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SB_OPEN_MIDI_INPUT_TRIGGER	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SB_OPEN_MIDI_OUTPUT_TRIGGER	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SB_MODE_HALT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SB_MODE_PLAYBACK_8	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SB_MODE_PLAYBACK_16	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SB_MODE_PLAYBACK	(SB_MODE_PLAYBACK_8 | SB_MODE_PLAYBACK_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SB_MODE_CAPTURE_8	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SB_MODE_CAPTURE_16	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SB_MODE_CAPTURE		(SB_MODE_CAPTURE_8 | SB_MODE_CAPTURE_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SB_RATE_LOCK_PLAYBACK	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SB_RATE_LOCK_CAPTURE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SB_RATE_LOCK		(SB_RATE_LOCK_PLAYBACK | SB_RATE_LOCK_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SB_MPU_INPUT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct snd_sb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned long port;		/* base port of DSP chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct resource *res_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned long mpu_port;		/* MPU port for SB DSP 4.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int irq;			/* IRQ number of DSP chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int dma8;			/* 8-bit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	int dma16;			/* 16-bit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned short version;		/* version of DSP chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	enum sb_hw_type hardware;	/* see to SB_HW_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned long alt_port;		/* alternate port (ALS4000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct pci_dev *pci;		/* ALS4000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	unsigned int open;		/* see to SB_OPEN_XXXX for sb8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 					/* also SNDRV_SB_CSP_MODE_XXX for sb16_csp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned int mode;		/* current mode of stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned int force_mode16;	/* force 16-bit mode of streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned int locked_rate;	/* sb16 duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned int playback_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int capture_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct timer_list midi_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned int p_dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned int p_period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	unsigned int c_dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	unsigned int c_period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	spinlock_t mixer_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	void *csp; /* used only when CONFIG_SND_SB16_CSP is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct snd_rawmidi_substream *midi_substream_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct snd_rawmidi_substream *midi_substream_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	irq_handler_t rmidi_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	spinlock_t open_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	spinlock_t midi_input_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct snd_info_entry *proc_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned char saved_regs[0x20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* I/O ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SBP(chip, x)		((chip)->port + s_b_SB_##x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SBP1(port, x)		((port) + s_b_SB_##x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define s_b_SB_RESET		0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define s_b_SB_READ		0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define s_b_SB_WRITE		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define s_b_SB_COMMAND		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define s_b_SB_STATUS		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define s_b_SB_DATA_AVAIL	0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define s_b_SB_DATA_AVAIL_16 	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define s_b_SB_MIXER_ADDR	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define s_b_SB_MIXER_DATA	0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define s_b_SB_OPL3_LEFT	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define s_b_SB_OPL3_RIGHT	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define s_b_SB_OPL3_BOTH	0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SB_DSP_OUTPUT		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SB_DSP_INPUT		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SB_DSP_BLOCK_SIZE	0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SB_DSP_HI_OUTPUT	0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SB_DSP_HI_INPUT		0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SB_DSP_LO_OUTPUT_AUTO	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SB_DSP_LO_INPUT_AUTO	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SB_DSP_HI_OUTPUT_AUTO	0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SB_DSP_HI_INPUT_AUTO	0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SB_DSP_IMMED_INT	0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SB_DSP_GET_VERSION	0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SB_DSP_SPEAKER_ON	0xd1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SB_DSP_SPEAKER_OFF	0xd3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SB_DSP_DMA8_OFF		0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SB_DSP_DMA8_ON		0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SB_DSP_DMA8_EXIT	0xda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SB_DSP_DMA16_OFF	0xd5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SB_DSP_DMA16_ON		0xd6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SB_DSP_DMA16_EXIT	0xd9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SB_DSP_SAMPLE_RATE	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SB_DSP_SAMPLE_RATE_OUT	0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SB_DSP_SAMPLE_RATE_IN	0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SB_DSP_MONO_8BIT	0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SB_DSP_MONO_16BIT	0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SB_DSP_STEREO_8BIT	0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SB_DSP_STEREO_16BIT	0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SB_DSP_MIDI_INPUT_IRQ	0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SB_DSP_MIDI_UART_IRQ	0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SB_DSP_MIDI_OUTPUT	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SB_DSP4_OUT8_AI		0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SB_DSP4_IN8_AI		0xce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SB_DSP4_OUT16_AI	0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SB_DSP4_IN16_AI		0xbe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SB_DSP4_MODE_UNS_MONO	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SB_DSP4_MODE_SIGN_MONO	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SB_DSP4_MODE_UNS_STEREO	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SB_DSP4_MODE_SIGN_STEREO 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SB_DSP4_OUTPUT		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SB_DSP4_INPUT_LEFT	0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SB_DSP4_INPUT_RIGHT	0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* registers for SB 2.0 mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SB_DSP20_MASTER_DEV	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SB_DSP20_PCM_DEV	0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SB_DSP20_CD_DEV		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SB_DSP20_FM_DEV		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* registers for SB PRO mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SB_DSP_MASTER_DEV	0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SB_DSP_PCM_DEV		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SB_DSP_LINE_DEV		0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SB_DSP_CD_DEV		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SB_DSP_FM_DEV		0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SB_DSP_MIC_DEV		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SB_DSP_CAPTURE_SOURCE	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SB_DSP_CAPTURE_FILT	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SB_DSP_PLAYBACK_FILT	0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SB_DSP_STEREO_SW	0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SB_DSP_MIXS_MIC0	0x00	/* same as MIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SB_DSP_MIXS_CD		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SB_DSP_MIXS_MIC		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SB_DSP_MIXS_LINE	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* registers (only for left channel) for SB 16 mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SB_DSP4_MASTER_DEV	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SB_DSP4_BASS_DEV	0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SB_DSP4_TREBLE_DEV	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SB_DSP4_SYNTH_DEV	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SB_DSP4_PCM_DEV		0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SB_DSP4_SPEAKER_DEV	0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SB_DSP4_LINE_DEV	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SB_DSP4_MIC_DEV		0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SB_DSP4_OUTPUT_SW	0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SB_DSP4_CD_DEV		0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SB_DSP4_IGAIN_DEV	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SB_DSP4_OGAIN_DEV	0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SB_DSP4_MIC_AGC		0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* additional registers for SB 16 mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SB_DSP4_IRQSETUP	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SB_DSP4_DMASETUP	0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SB_DSP4_IRQSTATUS	0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SB_DSP4_MPUSETUP	0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SB_DSP4_3DSE		0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Registers for DT-019x / ALS-007 mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SB_DT019X_MASTER_DEV	0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SB_DT019X_PCM_DEV	0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SB_DT019X_SYNTH_DEV	0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SB_DT019X_CD_DEV	0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SB_DT019X_MIC_DEV	0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SB_DT019X_SPKR_DEV	0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SB_DT019X_LINE_DEV	0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SB_DT019X_OUTPUT_SW2	0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SB_DT019X_CAPTURE_SW	0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SB_DT019X_CAP_CD	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SB_DT019X_CAP_MIC	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SB_DT019X_CAP_LINE	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SB_DT019X_CAP_SYNTH	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SB_DT019X_CAP_MAIN	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SB_ALS4000_MONO_IO_CTRL	0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SB_ALS4000_OUT_MIXER_CTRL_2	0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SB_ALS4000_MIC_IN_GAIN	0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SB_ALS4000_ANALOG_REFRNC_VOLT_CTRL 0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SB_ALS4000_FMDAC	0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SB_ALS4000_3D_SND_FX	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SB_ALS4000_3D_TIME_DELAY	0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SB_ALS4000_3D_AUTO_MUTE	0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SB_ALS4000_ANALOG_BLOCK_CTRL 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SB_ALS4000_3D_DELAYLINE_PATTERN 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SB_ALS4000_CR3_CONFIGURATION	0xc3 /* bit 7 is Digital Loop Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SB_ALS4000_QSOUND	0xdb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* IRQ setting bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SB_IRQSETUP_IRQ9	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SB_IRQSETUP_IRQ5	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SB_IRQSETUP_IRQ7	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SB_IRQSETUP_IRQ10	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* IRQ types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SB_IRQTYPE_8BIT		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SB_IRQTYPE_16BIT	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SB_IRQTYPE_MPUIN	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ALS4K_IRQTYPE_CR1E_DMA	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* DMA setting bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SB_DMASETUP_DMA0	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SB_DMASETUP_DMA1	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SB_DMASETUP_DMA3	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SB_DMASETUP_DMA5	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SB_DMASETUP_DMA6	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SB_DMASETUP_DMA7	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline void snd_sb_ack_8bit(struct snd_sb *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	inb(SBP(chip, DATA_AVAIL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline void snd_sb_ack_16bit(struct snd_sb *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	inb(SBP(chip, DATA_AVAIL_16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* sb_common.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int snd_sbdsp_command(struct snd_sb *chip, unsigned char val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int snd_sbdsp_get_byte(struct snd_sb *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int snd_sbdsp_reset(struct snd_sb *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int snd_sbdsp_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		     unsigned long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		     int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		     irq_handler_t irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		     int dma8, int dma16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		     unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		     struct snd_sb **r_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* sb_mixer.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void snd_sbmixer_write(struct snd_sb *chip, unsigned char reg, unsigned char data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned char snd_sbmixer_read(struct snd_sb *chip, unsigned char reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int snd_sbmixer_new(struct snd_sb *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void snd_sbmixer_suspend(struct snd_sb *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void snd_sbmixer_resume(struct snd_sb *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* sb8_init.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int snd_sb8dsp_pcm(struct snd_sb *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* sb8.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) irqreturn_t snd_sb8dsp_interrupt(struct snd_sb *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int snd_sb8_playback_open(struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int snd_sb8_capture_open(struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int snd_sb8_playback_close(struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int snd_sb8_capture_close(struct snd_pcm_substream *substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* midi8.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) irqreturn_t snd_sb8dsp_midi_interrupt(struct snd_sb *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int snd_sb8dsp_midi(struct snd_sb *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* sb16_init.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int snd_sb16dsp_pcm(struct snd_sb *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) const struct snd_pcm_ops *snd_sb16dsp_get_pcm_ops(int direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int snd_sb16dsp_configure(struct snd_sb *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* sb16.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) irqreturn_t snd_sb16dsp_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* exported mixer stuffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	SB_MIX_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	SB_MIX_DOUBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	SB_MIX_INPUT_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	SB_MIX_CAPTURE_PRO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	SB_MIX_CAPTURE_DT019X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	SB_MIX_MONO_CAPTURE_ALS4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SB_MIXVAL_DOUBLE(left_reg, right_reg, left_shift, right_shift, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)   ((left_reg) | ((right_reg) << 8) | ((left_shift) << 16) | ((right_shift) << 19) | ((mask) << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SB_MIXVAL_SINGLE(reg, shift, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)   ((reg) | ((shift) << 16) | ((mask) << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)   ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int snd_sbmixer_add_ctl(struct snd_sb *chip, const char *name, int index, int type, unsigned long value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* for ease of use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct sbmix_elem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	unsigned long private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SB_SINGLE(xname, reg, shift, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)   .type = SB_MIX_SINGLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)   .private_value = SB_MIXVAL_SINGLE(reg, shift, mask) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SB_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)   .type = SB_MIX_DOUBLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)   .private_value = SB_MIXVAL_DOUBLE(left_reg, right_reg, left_shift, right_shift, mask) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)   .type = SB_MIX_INPUT_SW, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)   .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static inline int snd_sbmixer_add_ctl_elem(struct snd_sb *chip, const struct sbmix_elem *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return snd_sbmixer_add_ctl(chip, c->name, 0, c->type, c->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #endif /* __SOUND_SB_H */