^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SOUND_OPL3_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SOUND_OPL3_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Definitions of the OPL-3 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Hannu Savolainen 1993-1996
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The OPL-3 mode is switched on by writing 0x01, to the offset 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * of the right side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Another special register at the right side is at offset 4. It contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * a bit mask defining which voices are used as 4 OP voices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The percussive mode is implemented in the left side only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * With the above exceptions the both sides can be operated independently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * A 4 OP voice can be created by setting the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * bit at offset 4 of the right side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * For example setting the rightmost bit (0x01) changes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * first voice on the right side to the 4 OP mode. The fourth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * voice is made inaccessible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * If a voice is set to the 2 OP mode, it works like 2 OP modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * of the original YM3812 (AdLib). In addition the voice can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * be connected the left, right or both stereo channels. It can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * even be left unconnected. This works with 4 OP voices also.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * The stereo connection bits are located in the FEEDBACK_CONNECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * register of the voice (0xC0-0xC8). In 4 OP voices these bits are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * in the second half of the voice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <sound/hwdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <sound/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <sound/seq_midi_emul.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <sound/seq_oss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <sound/seq_oss_legacy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <sound/seq_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <sound/asound_fm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Register numbers for the global registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OPL3_REG_TEST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OPL3_ENABLE_WAVE_SELECT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OPL3_REG_TIMER1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OPL3_REG_TIMER2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OPL3_REG_TIMER_CONTROL 0x04 /* Left side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OPL3_IRQ_RESET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OPL3_TIMER1_MASK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OPL3_TIMER2_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OPL3_TIMER1_START 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OPL3_TIMER2_START 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OPL3_REG_CONNECTION_SELECT 0x04 /* Right side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OPL3_LEFT_4OP_0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OPL3_LEFT_4OP_1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OPL3_LEFT_4OP_2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OPL3_RIGHT_4OP_0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OPL3_RIGHT_4OP_1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OPL3_RIGHT_4OP_2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OPL3_REG_MODE 0x05 /* Right side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OPL3_OPL3_ENABLE 0x01 /* OPL3 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OPL3_OPL4_ENABLE 0x02 /* OPL4 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OPL3_REG_KBD_SPLIT 0x08 /* Left side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OPL3_COMPOSITE_SINE_WAVE_MODE 0x80 /* Don't use with OPL-3? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OPL3_KEYBOARD_SPLIT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OPL3_REG_PERCUSSION 0xbd /* Left side only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OPL3_TREMOLO_DEPTH 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OPL3_VIBRATO_DEPTH 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OPL3_PERCUSSION_ENABLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OPL3_BASSDRUM_ON 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OPL3_SNAREDRUM_ON 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OPL3_TOMTOM_ON 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OPL3_CYMBAL_ON 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OPL3_HIHAT_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Offsets to the register banks for operators. To get the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * register number just add the operator offset to the bank offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * AM/VIB/EG/KSR/Multiple (0x20 to 0x35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OPL3_REG_AM_VIB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OPL3_TREMOLO_ON 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OPL3_VIBRATO_ON 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OPL3_SUSTAIN_ON 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OPL3_KSR 0x10 /* Key scaling rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OPL3_MULTIPLE_MASK 0x0f /* Frequency multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * KSL/Total level (0x40 to 0x55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OPL3_REG_KSL_LEVEL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OPL3_KSL_MASK 0xc0 /* Envelope scaling bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OPL3_TOTAL_LEVEL_MASK 0x3f /* Strength (volume) of OP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Attack / Decay rate (0x60 to 0x75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OPL3_REG_ATTACK_DECAY 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OPL3_ATTACK_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OPL3_DECAY_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Sustain level / Release rate (0x80 to 0x95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OPL3_REG_SUSTAIN_RELEASE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OPL3_SUSTAIN_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OPL3_RELEASE_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Wave select (0xE0 to 0xF5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OPL3_REG_WAVE_SELECT 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OPL3_WAVE_SELECT_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Offsets to the register banks for voices. Just add to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * voice number to get the register number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * F-Number low bits (0xA0 to 0xA8).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OPL3_REG_FNUM_LOW 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * F-number high bits / Key on / Block (octave) (0xB0 to 0xB8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OPL3_REG_KEYON_BLOCK 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OPL3_KEYON_BIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OPL3_BLOCKNUM_MASK 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OPL3_FNUM_HIGH_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Feedback / Connection (0xc0 to 0xc8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * These registers have two new bits when the OPL-3 mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * is selected. These bits controls connecting the voice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * to the stereo channels. For 4 OP voices this bit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * defined in the second half of the voice (add 3 to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * register offset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * For 4 OP voices the connection bit is used in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * both halves (gives 4 ways to connect the operators).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OPL3_REG_FEEDBACK_CONNECTION 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OPL3_FEEDBACK_MASK 0x0e /* Valid just for 1st OP of a voice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OPL3_CONNECTION_BIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * In the 4 OP mode there is four possible configurations how the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * operators can be connected together (in 2 OP modes there is just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * AM or FM). The 4 OP connection mode is defined by the rightmost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * bit of the FEEDBACK_CONNECTION (0xC0-0xC8) on the both halves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * First half Second half Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * +---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * v |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * 0 0 >+-1-+--2--3--4-->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * +---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * 0 1 >+-1-+--2-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * |->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * >--3----4-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * +---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * 1 0 >+-1-+-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * |->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * >--2--3--4-+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * +---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * 1 1 >+-1-+--+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * >--2--3-+->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * >--4----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OPL3_STEREO_BITS 0x30 /* OPL-3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OPL3_VOICE_TO_LEFT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OPL3_VOICE_TO_RIGHT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OPL3_LEFT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OPL3_RIGHT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OPL3_HW_AUTO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OPL3_HW_OPL2 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OPL3_HW_OPL3 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OPL3_HW_OPL3_SV 0x0301 /* S3 SonicVibes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OPL3_HW_OPL3_CS 0x0302 /* CS4232/CS4236+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OPL3_HW_OPL3_FM801 0x0303 /* FM801 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OPL3_HW_OPL3_CS4281 0x0304 /* CS4281 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OPL3_HW_OPL4 0x0400 /* YMF278B/YMF295 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OPL3_HW_OPL4_ML 0x0401 /* YMF704/YMF721 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OPL3_HW_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MAX_OPL2_VOICES 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MAX_OPL3_VOICES 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct snd_opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Instrument record, aka "Patch"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* FM operator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct fm_operator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned char am_vib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned char ksl_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned char attack_decay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned char sustain_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned char wave_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } __attribute__((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Instrument data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct fm_instrument {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct fm_operator op[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned char feedback_connection[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned char echo_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned char echo_atten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned char chorus_spread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned char trnsps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned char fix_dur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned char modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned char fix_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define FM_PATCH_OPL2 0x01 /* OPL2 2 operators FM instrument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define FM_PATCH_OPL3 0x02 /* OPL3 4 operators FM instrument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Instrument record */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct fm_patch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned char prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned char bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned char type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct fm_instrument inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) char name[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct fm_patch *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * A structure to keep track of each hardware voice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct snd_opl3_voice {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int state; /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SNDRV_OPL3_ST_OFF 0 /* Not playing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SNDRV_OPL3_ST_ON_2OP 1 /* 2op voice is allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SNDRV_OPL3_ST_ON_4OP 2 /* 4op voice is allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SNDRV_OPL3_ST_NOT_AVAIL -1 /* voice is not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int time; /* An allocation time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned char note; /* Note currently assigned to this voice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long note_off; /* note-off time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int note_off_check; /* check note-off time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned char keyon_reg; /* KON register shadow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct snd_midi_channel *chan; /* Midi channel for this note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct snd_opl3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned long l_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned long r_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct resource *res_l_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct resource *res_r_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned short hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* hardware access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void (*command) (struct snd_opl3 * opl3, unsigned short cmd, unsigned char val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned short timer_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int seq_dev_num; /* sequencer device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct snd_timer *timer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct snd_timer *timer2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) spinlock_t timer_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void (*private_free)(struct snd_opl3 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct snd_hwdep *hwdep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct snd_card *card; /* The card that this belongs to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned char fm_mode; /* OPL mode, see SNDRV_DM_FM_MODE_XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned char rhythm; /* percussion mode flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned char max_voices; /* max number of voices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #if IS_ENABLED(CONFIG_SND_SEQUENCER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SNDRV_OPL3_MODE_SYNTH 0 /* OSS - voices allocated by application */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SNDRV_OPL3_MODE_SEQ 1 /* ALSA - driver handles voice allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int synth_mode; /* synth mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int seq_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct snd_seq_device *seq_dev; /* sequencer device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct snd_midi_channel_set * chset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct snd_seq_device *oss_seq_dev; /* OSS sequencer device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct snd_midi_channel_set * oss_chset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define OPL3_PATCH_HASH_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct fm_patch *patch_table[OPL3_PATCH_HASH_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct snd_opl3_voice voices[MAX_OPL3_VOICES]; /* Voices (OPL3 'channel') */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int use_time; /* allocation counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned short connection_reg; /* connection reg shadow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned char drum_reg; /* percussion reg shadow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) spinlock_t voice_lock; /* Lock for voice access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct timer_list tlist; /* timer for note-offs and effects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int sys_timer_status; /* system timer run status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) spinlock_t sys_timer_lock; /* Lock for system timer access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* opl3.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) void snd_opl3_interrupt(struct snd_hwdep * hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int snd_opl3_new(struct snd_card *card, unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct snd_opl3 **ropl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int snd_opl3_init(struct snd_opl3 *opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int snd_opl3_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned long l_port, unsigned long r_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int integrated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct snd_opl3 ** opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int snd_opl3_timer_new(struct snd_opl3 * opl3, int timer1_dev, int timer2_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int snd_opl3_hwdep_new(struct snd_opl3 * opl3, int device, int seq_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct snd_hwdep ** rhwdep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* opl3_synth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int snd_opl3_open(struct snd_hwdep * hw, struct file *file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int snd_opl3_ioctl(struct snd_hwdep * hw, struct file *file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int cmd, unsigned long arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int snd_opl3_release(struct snd_hwdep * hw, struct file *file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) void snd_opl3_reset(struct snd_opl3 * opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #if IS_ENABLED(CONFIG_SND_SEQUENCER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) long snd_opl3_write(struct snd_hwdep *hw, const char __user *buf, long count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) loff_t *offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int snd_opl3_load_patch(struct snd_opl3 *opl3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int prog, int bank, int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) const unsigned char *ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) const unsigned char *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct fm_patch *snd_opl3_find_patch(struct snd_opl3 *opl3, int prog, int bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int create_patch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) void snd_opl3_clear_patches(struct snd_opl3 *opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define snd_opl3_write NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static inline void snd_opl3_clear_patches(struct snd_opl3 *opl3) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #endif /* __SOUND_OPL3_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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