^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SOUND_MPU401_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SOUND_MPU401_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Header file for MPU-401 and compatible cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MPU401_HW_MPU401 1 /* native MPU401 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MPU401_HW_SB 2 /* SoundBlaster MPU-401 UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MPU401_HW_ES1688 3 /* AudioDrive ES1688 MPU-401 UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MPU401_HW_OPL3SA2 4 /* Yamaha OPL3-SA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MPU401_HW_SONICVIBES 5 /* S3 SonicVibes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MPU401_HW_CS4232 6 /* CS4232 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MPU401_HW_ES18XX 7 /* AudioDrive ES18XX MPU-401 UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MPU401_HW_FM801 8 /* ForteMedia FM801 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MPU401_HW_TRID4DWAVE 9 /* Trident 4DWave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MPU401_HW_AZT2320 10 /* Aztech AZT2320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPU401_HW_ALS100 11 /* Avance Logic ALS100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPU401_HW_ICE1712 12 /* Envy24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPU401_HW_VIA686A 13 /* VIA 82C686A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPU401_HW_YMFPCI 14 /* YMF DS-XG PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPU401_HW_CMIPCI 15 /* CMIPCI MPU-401 UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MPU401_HW_ALS4000 16 /* Avance Logic ALS4000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MPU401_HW_INTEL8X0 17 /* Intel8x0 driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MPU401_HW_PC98II 18 /* Roland PC98II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MPU401_HW_AUREAL 19 /* Aureal Vortex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MPU401_INFO_INPUT (1 << 0) /* input stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MPU401_INFO_OUTPUT (1 << 1) /* output stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MPU401_INFO_INTEGRATED (1 << 2) /* integrated h/w port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MPU401_INFO_MMIO (1 << 3) /* MMIO access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MPU401_INFO_TX_IRQ (1 << 4) /* independent TX irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPU401_INFO_IRQ_HOOK (1 << 5) /* mpu401 irq handler is called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) from driver irq handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MPU401_INFO_NO_ACK (1 << 6) /* No ACK cmd needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MPU401_INFO_USE_TIMER (1 << 15) /* internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MPU401_MODE_BIT_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPU401_MODE_BIT_OUTPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPU401_MODE_BIT_INPUT_TRIGGER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MPU401_MODE_BIT_OUTPUT_TRIGGER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MPU401_MODE_INPUT (1<<MPU401_MODE_BIT_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MPU401_MODE_OUTPUT (1<<MPU401_MODE_BIT_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MPU401_MODE_INPUT_TRIGGER (1<<MPU401_MODE_BIT_INPUT_TRIGGER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MPU401_MODE_OUTPUT_TRIGGER (1<<MPU401_MODE_BIT_OUTPUT_TRIGGER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPU401_MODE_INPUT_TIMER (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MPU401_MODE_OUTPUT_TIMER (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct snd_mpu401 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned short hardware; /* MPU401_HW_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int info_flags; /* MPU401_INFO_XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long port; /* base port of MPU-401 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long cport; /* port + 1 (usually) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct resource *res; /* port resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int irq; /* IRQ number of MPU-401 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long mode; /* MPU401_MODE_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int timer_invoked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int (*open_input) (struct snd_mpu401 * mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void (*close_input) (struct snd_mpu401 * mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int (*open_output) (struct snd_mpu401 * mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void (*close_output) (struct snd_mpu401 * mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct snd_rawmidi_substream *substream_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct snd_rawmidi_substream *substream_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) spinlock_t input_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) spinlock_t output_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) spinlock_t timer_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void (*write) (struct snd_mpu401 * mpu, unsigned char data, unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned char (*read) (struct snd_mpu401 *mpu, unsigned long addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* I/O ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MPU401C(mpu) (mpu)->cport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MPU401D(mpu) (mpu)->port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * control register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* read MPU401C() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MPU401_RX_EMPTY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MPU401_TX_FULL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* write MPU401C() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MPU401_RESET 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MPU401_ENTER_UART 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* read MPU401D() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MPU401_ACK 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) irqreturn_t snd_mpu401_uart_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) irqreturn_t snd_mpu401_uart_interrupt_tx(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int snd_mpu401_uart_new(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int info_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct snd_rawmidi ** rrawmidi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif /* __SOUND_MPU401_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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