^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Platform data for MAX98095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Maxim Integrated Products
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __SOUND_MAX98095_PDATA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __SOUND_MAX98095_PDATA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Equalizer filter response configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct max98095_eq_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u16 band1[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u16 band2[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u16 band3[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u16 band4[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u16 band5[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Biquad filter response configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct max98095_biquad_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u16 band1[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u16 band2[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* codec platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct max98095_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Equalizers for DAI1 and DAI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct max98095_eq_cfg *eq_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int eq_cfgcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Biquad filter for DAI1 and DAI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct max98095_biquad_cfg *bq_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int bq_cfgcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Analog/digital microphone configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 0 = analog microphone input (normal setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 1 = digital microphone input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int digmic_left_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int digmic_right_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Pin5 is the mechanical method of sensing jack insertion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * but it is something that might not be supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 0 = PIN5 not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 1 = PIN5 supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int jack_detect_pin5en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Slew amount for jack detection. Calculated as 4 * (delay + 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Default delay is 24 to get a time of 100ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int jack_detect_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif