Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Platform data for Madera codec driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2016-2019 Cirrus Logic, Inc. and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *                         Cirrus Logic International Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef MADERA_CODEC_PDATA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MADERA_CODEC_PDATA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MADERA_MAX_INPUT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MADERA_MAX_MUXED_CHANNELS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MADERA_MAX_OUTPUT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MADERA_MAX_AIF			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MADERA_MAX_PDM_SPK		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MADERA_MAX_DSP			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * struct madera_codec_pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * @max_channels_clocked: Maximum number of channels that I2S clocks will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *			  generated for. Useful when clock master for systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *			  where the I2S bus has multiple data lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * @dmic_ref:		  Indicates how the MICBIAS pins have been externally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  *			  connected to DMICs on each input. A value of 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  *			  indicates MICVDD and is the default. Other values are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  *			  For CS47L35 one of the CS47L35_DMIC_REF_xxx values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  *			  For all other codecs one of the MADERA_DMIC_REF_xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  *			  Also see the datasheet for a description of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  *			  INn_DMIC_SUP field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * @inmode:		  Mode for the ADC inputs. One of the MADERA_INMODE_xxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  *			  values. Two-dimensional array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  *			  [input_number][channel number], with four slots per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  *			  input in the order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  *			  [n][0]=INnAL [n][1]=INnAR [n][2]=INnBL [n][3]=INnBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * @out_mono:		  For each output set the value to TRUE to indicate that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  *			  the output is mono. [0]=OUT1, [1]=OUT2, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * @pdm_fmt:		  PDM speaker data format. See the PDM_SPKn_FMT field in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  *			  the datasheet for a description of this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  * @pdm_mute:		  PDM mute format. See the PDM_SPKn_CTRL_1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  *			  in the datasheet for a description of this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct madera_codec_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	u32 max_channels_clocked[MADERA_MAX_AIF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	u32 dmic_ref[MADERA_MAX_INPUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	u32 inmode[MADERA_MAX_INPUT][MADERA_MAX_MUXED_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	bool out_mono[MADERA_MAX_OUTPUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	u32 pdm_fmt[MADERA_MAX_PDM_SPK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	u32 pdm_mute[MADERA_MAX_PDM_SPK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif