^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * HD-audio codec verbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __SOUND_HDA_VERBS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __SOUND_HDA_VERBS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AC_NODE_ROOT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * function group types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) AC_GRP_AUDIO_FUNCTION = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) AC_GRP_MODEM_FUNCTION = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * widget types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) AC_WID_AUD_OUT, /* Audio Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) AC_WID_AUD_IN, /* Audio In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) AC_WID_AUD_MIX, /* Audio Mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) AC_WID_AUD_SEL, /* Audio Selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) AC_WID_PIN, /* Pin Complex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) AC_WID_POWER, /* Power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) AC_WID_VOL_KNB, /* Volume Knob */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) AC_WID_BEEP, /* Beep Generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) AC_WID_VENDOR = 0x0f /* Vendor specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * GET verbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AC_VERB_GET_STREAM_FORMAT 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AC_VERB_GET_AMP_GAIN_MUTE 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AC_VERB_GET_PROC_COEF 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AC_VERB_GET_COEF_INDEX 0x0d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AC_VERB_PARAMETERS 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AC_VERB_GET_CONNECT_SEL 0x0f01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AC_VERB_GET_CONNECT_LIST 0x0f02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AC_VERB_GET_PROC_STATE 0x0f03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AC_VERB_GET_SDI_SELECT 0x0f04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AC_VERB_GET_POWER_STATE 0x0f05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AC_VERB_GET_CONV 0x0f06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AC_VERB_GET_PIN_WIDGET_CONTROL 0x0f07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AC_VERB_GET_UNSOLICITED_RESPONSE 0x0f08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AC_VERB_GET_PIN_SENSE 0x0f09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AC_VERB_GET_BEEP_CONTROL 0x0f0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AC_VERB_GET_EAPD_BTLENABLE 0x0f0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AC_VERB_GET_DIGI_CONVERT_1 0x0f0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AC_VERB_GET_DIGI_CONVERT_2 0x0f0e /* unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AC_VERB_GET_VOLUME_KNOB_CONTROL 0x0f0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* f10-f1a: GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AC_VERB_GET_GPIO_DATA 0x0f15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AC_VERB_GET_GPIO_MASK 0x0f16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AC_VERB_GET_GPIO_DIRECTION 0x0f17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AC_VERB_GET_GPIO_WAKE_MASK 0x0f18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK 0x0f19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AC_VERB_GET_GPIO_STICKY_MASK 0x0f1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AC_VERB_GET_CONFIG_DEFAULT 0x0f1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* f20: AFG/MFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AC_VERB_GET_SUBSYSTEM_ID 0x0f20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AC_VERB_GET_STRIPE_CONTROL 0x0f24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AC_VERB_GET_CVT_CHAN_COUNT 0x0f2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AC_VERB_GET_HDMI_DIP_SIZE 0x0f2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AC_VERB_GET_HDMI_ELDD 0x0f2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AC_VERB_GET_HDMI_DIP_INDEX 0x0f30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AC_VERB_GET_HDMI_DIP_DATA 0x0f31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AC_VERB_GET_HDMI_DIP_XMIT 0x0f32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AC_VERB_GET_HDMI_CP_CTRL 0x0f33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AC_VERB_GET_HDMI_CHAN_SLOT 0x0f34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AC_VERB_GET_DEVICE_SEL 0xf35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AC_VERB_GET_DEVICE_LIST 0xf36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * SET verbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AC_VERB_SET_STREAM_FORMAT 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AC_VERB_SET_AMP_GAIN_MUTE 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AC_VERB_SET_PROC_COEF 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AC_VERB_SET_COEF_INDEX 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AC_VERB_SET_CONNECT_SEL 0x701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AC_VERB_SET_PROC_STATE 0x703
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AC_VERB_SET_SDI_SELECT 0x704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AC_VERB_SET_POWER_STATE 0x705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AC_VERB_SET_CHANNEL_STREAMID 0x706
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AC_VERB_SET_PIN_WIDGET_CONTROL 0x707
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AC_VERB_SET_UNSOLICITED_ENABLE 0x708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AC_VERB_SET_PIN_SENSE 0x709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AC_VERB_SET_BEEP_CONTROL 0x70a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AC_VERB_SET_EAPD_BTLENABLE 0x70c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AC_VERB_SET_DIGI_CONVERT_1 0x70d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AC_VERB_SET_DIGI_CONVERT_2 0x70e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AC_VERB_SET_DIGI_CONVERT_3 0x73e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AC_VERB_SET_VOLUME_KNOB_CONTROL 0x70f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AC_VERB_SET_GPIO_DATA 0x715
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AC_VERB_SET_GPIO_MASK 0x716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AC_VERB_SET_GPIO_DIRECTION 0x717
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AC_VERB_SET_GPIO_WAKE_MASK 0x718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK 0x719
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AC_VERB_SET_GPIO_STICKY_MASK 0x71a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_0 0x71c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_1 0x71d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_2 0x71e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AC_VERB_SET_CONFIG_DEFAULT_BYTES_3 0x71f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AC_VERB_SET_EAPD 0x788
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AC_VERB_SET_CODEC_RESET 0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AC_VERB_SET_STRIPE_CONTROL 0x724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AC_VERB_SET_CVT_CHAN_COUNT 0x72d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AC_VERB_SET_HDMI_DIP_INDEX 0x730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AC_VERB_SET_HDMI_DIP_DATA 0x731
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AC_VERB_SET_HDMI_DIP_XMIT 0x732
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AC_VERB_SET_HDMI_CP_CTRL 0x733
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AC_VERB_SET_HDMI_CHAN_SLOT 0x734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AC_VERB_SET_DEVICE_SEL 0x735
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Parameter IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AC_PAR_VENDOR_ID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AC_PAR_SUBSYSTEM_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AC_PAR_REV_ID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AC_PAR_NODE_COUNT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AC_PAR_FUNCTION_TYPE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AC_PAR_AUDIO_FG_CAP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AC_PAR_AUDIO_WIDGET_CAP 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AC_PAR_PCM 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AC_PAR_STREAM 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AC_PAR_PIN_CAP 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AC_PAR_AMP_IN_CAP 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AC_PAR_CONNLIST_LEN 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AC_PAR_POWER_STATE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AC_PAR_PROC_CAP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AC_PAR_GPIO_CAP 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AC_PAR_AMP_OUT_CAP 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AC_PAR_VOL_KNB_CAP 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AC_PAR_DEVLIST_LEN 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AC_PAR_HDMI_LPCM_CAP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * AC_VERB_PARAMETERS results (32bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Function Group Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AC_FGT_TYPE (0xff<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AC_FGT_TYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AC_FGT_UNSOL_CAP (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Audio Function Group Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AC_AFG_OUT_DELAY (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AC_AFG_IN_DELAY (0xf<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AC_AFG_BEEP_GEN (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Audio Widget Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AC_WCAP_STEREO (1<<0) /* stereo I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AC_WCAP_FORMAT_OVRD (1<<4) /* format override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AC_WCAP_STRIPE (1<<5) /* stripe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AC_WCAP_PROC_WID (1<<6) /* Proc Widget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AC_WCAP_UNSOL_CAP (1<<7) /* Unsol capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AC_WCAP_CONN_LIST (1<<8) /* connection list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AC_WCAP_DIGITAL (1<<9) /* digital I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define AC_WCAP_POWER (1<<10) /* power control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AC_WCAP_LR_SWAP (1<<11) /* L/R swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AC_WCAP_CP_CAPS (1<<12) /* content protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AC_WCAP_CHAN_CNT_EXT (7<<13) /* channel count ext */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AC_WCAP_DELAY (0xf<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AC_WCAP_DELAY_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AC_WCAP_TYPE (0xf<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AC_WCAP_TYPE_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* supported PCM rates and bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AC_SUPPCM_RATES (0xfff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AC_SUPPCM_BITS_8 (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AC_SUPPCM_BITS_16 (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AC_SUPPCM_BITS_20 (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AC_SUPPCM_BITS_24 (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AC_SUPPCM_BITS_32 (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* supported PCM stream format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AC_SUPFMT_PCM (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AC_SUPFMT_FLOAT32 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AC_SUPFMT_AC3 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* GP I/O count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AC_GPIO_IO_COUNT (0xff<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AC_GPIO_O_COUNT (0xff<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AC_GPIO_O_COUNT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AC_GPIO_I_COUNT (0xff<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AC_GPIO_I_COUNT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AC_GPIO_UNSOLICITED (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AC_GPIO_WAKE (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Converter stream, channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AC_CONV_CHANNEL (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AC_CONV_STREAM (0xf<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AC_CONV_STREAM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Input converter SDI select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AC_SDI_SELECT (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* stream format id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AC_FMT_CHAN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AC_FMT_CHAN_MASK (0x0f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AC_FMT_BITS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AC_FMT_BITS_MASK (7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AC_FMT_BITS_8 (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AC_FMT_BITS_16 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AC_FMT_BITS_20 (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AC_FMT_BITS_24 (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AC_FMT_BITS_32 (4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AC_FMT_DIV_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AC_FMT_DIV_MASK (7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AC_FMT_MULT_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AC_FMT_MULT_MASK (7 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AC_FMT_BASE_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AC_FMT_BASE_48K (0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define AC_FMT_BASE_44K (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AC_FMT_TYPE_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AC_FMT_TYPE_PCM (0 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AC_FMT_TYPE_NON_PCM (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Unsolicited response control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AC_UNSOL_TAG (0x3f<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AC_UNSOL_ENABLED (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AC_USRSP_EN AC_UNSOL_ENABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Unsolicited responses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AC_UNSOL_RES_TAG (0x3f<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AC_UNSOL_RES_TAG_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AC_UNSOL_RES_SUBTAG (0x1f<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AC_UNSOL_RES_SUBTAG_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AC_UNSOL_RES_DE (0x3f<<15) /* Device Entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * (for DP1.2 MST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AC_UNSOL_RES_DE_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AC_UNSOL_RES_IA (1<<2) /* Inactive (for DP1.2 MST) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AC_UNSOL_RES_ELDV (1<<1) /* ELD Data valid (for HDMI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define AC_UNSOL_RES_PD (1<<0) /* pinsense detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AC_UNSOL_RES_CP_STATE (1<<1) /* content protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define AC_UNSOL_RES_CP_READY (1<<0) /* content protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Pin widget capabilies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AC_PINCAP_IMP_SENSE (1<<0) /* impedance sense capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AC_PINCAP_TRIG_REQ (1<<1) /* trigger required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define AC_PINCAP_PRES_DETECT (1<<2) /* presence detect capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AC_PINCAP_HP_DRV (1<<3) /* headphone drive capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define AC_PINCAP_OUT (1<<4) /* output capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AC_PINCAP_IN (1<<5) /* input capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define AC_PINCAP_BALANCE (1<<6) /* balanced I/O capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Note: This LR_SWAP pincap is defined in the Realtek ALC883 specification,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * but is marked reserved in the Intel HDA specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define AC_PINCAP_LR_SWAP (1<<7) /* L/R swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Note: The same bit as LR_SWAP is newly defined as HDMI capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * in HD-audio specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define AC_PINCAP_HDMI (1<<7) /* HDMI pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AC_PINCAP_DP (1<<24) /* DisplayPort pin, can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * coexist with AC_PINCAP_HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define AC_PINCAP_VREF (0x37<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define AC_PINCAP_VREF_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define AC_PINCAP_EAPD (1<<16) /* EAPD capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define AC_PINCAP_HBR (1<<27) /* High Bit Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Vref status (used in pin cap) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define AC_PINCAP_VREF_50 (1<<1) /* 50% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define AC_PINCAP_VREF_GRD (1<<2) /* ground */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define AC_PINCAP_VREF_80 (1<<4) /* 80% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define AC_PINCAP_VREF_100 (1<<5) /* 100% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Amplifier capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AC_AMPCAP_OFFSET (0x7f<<0) /* 0dB offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define AC_AMPCAP_OFFSET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define AC_AMPCAP_NUM_STEPS (0x7f<<8) /* number of steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define AC_AMPCAP_NUM_STEPS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define AC_AMPCAP_STEP_SIZE (0x7f<<16) /* step size 0-32dB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * in 0.25dB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define AC_AMPCAP_STEP_SIZE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define AC_AMPCAP_MUTE (1<<31) /* mute capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define AC_AMPCAP_MUTE_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* driver-specific amp-caps: using bits 24-30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define AC_AMPCAP_MIN_MUTE (1 << 30) /* min-volume = mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Connection list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define AC_CLIST_LENGTH (0x7f<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define AC_CLIST_LONG (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Supported power status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define AC_PWRST_D0SUP (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define AC_PWRST_D1SUP (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define AC_PWRST_D2SUP (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define AC_PWRST_D3SUP (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define AC_PWRST_D3COLDSUP (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define AC_PWRST_S3D3COLDSUP (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define AC_PWRST_CLKSTOP (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define AC_PWRST_EPSS (1U<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Power state values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define AC_PWRST_SETTING (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define AC_PWRST_ACTUAL (0xf<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define AC_PWRST_ACTUAL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define AC_PWRST_D0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define AC_PWRST_D1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define AC_PWRST_D2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define AC_PWRST_D3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define AC_PWRST_ERROR (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define AC_PWRST_CLK_STOP_OK (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define AC_PWRST_SETTING_RESET (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Processing capabilies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define AC_PCAP_BENIGN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define AC_PCAP_NUM_COEF (0xff<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define AC_PCAP_NUM_COEF_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Volume knobs capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define AC_KNBCAP_NUM_STEPS (0x7f<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define AC_KNBCAP_DELTA (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* HDMI LPCM capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define AC_LPCMCAP_48K_CP_CHNS (0x0f<<0) /* max channels w/ CP-on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define AC_LPCMCAP_48K_NO_CHNS (0x0f<<4) /* max channels w/o CP-on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define AC_LPCMCAP_48K_20BIT (1<<8) /* 20b bitrate supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define AC_LPCMCAP_48K_24BIT (1<<9) /* 24b bitrate supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define AC_LPCMCAP_96K_CP_CHNS (0x0f<<10) /* max channels w/ CP-on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define AC_LPCMCAP_96K_NO_CHNS (0x0f<<14) /* max channels w/o CP-on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define AC_LPCMCAP_96K_20BIT (1<<18) /* 20b bitrate supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define AC_LPCMCAP_96K_24BIT (1<<19) /* 24b bitrate supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define AC_LPCMCAP_192K_CP_CHNS (0x0f<<20) /* max channels w/ CP-on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define AC_LPCMCAP_192K_NO_CHNS (0x0f<<24) /* max channels w/o CP-on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define AC_LPCMCAP_192K_20BIT (1<<28) /* 20b bitrate supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define AC_LPCMCAP_192K_24BIT (1<<29) /* 24b bitrate supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define AC_LPCMCAP_44K (1<<30) /* 44.1kHz support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define AC_LPCMCAP_44K_MS (1<<31) /* 44.1kHz-multiplies support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Display pin's device list length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define AC_DEV_LIST_LEN_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define AC_MAX_DEV_LIST_LEN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Control Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Amp gain/mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define AC_AMP_MUTE (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define AC_AMP_GAIN (0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define AC_AMP_GET_INDEX (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define AC_AMP_GET_LEFT (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define AC_AMP_GET_RIGHT (0<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define AC_AMP_GET_OUTPUT (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define AC_AMP_GET_INPUT (0<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define AC_AMP_SET_INDEX (0xf<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define AC_AMP_SET_INDEX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define AC_AMP_SET_RIGHT (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define AC_AMP_SET_LEFT (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define AC_AMP_SET_INPUT (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define AC_AMP_SET_OUTPUT (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* DIGITAL1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define AC_DIG1_ENABLE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define AC_DIG1_V (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define AC_DIG1_VCFG (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define AC_DIG1_EMPHASIS (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define AC_DIG1_COPYRIGHT (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define AC_DIG1_NONAUDIO (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define AC_DIG1_PROFESSIONAL (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define AC_DIG1_LEVEL (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* DIGITAL2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define AC_DIG2_CC (0x7f<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* DIGITAL3 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define AC_DIG3_ICT (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define AC_DIG3_KAE (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Pin widget control - 8bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define AC_PINCTL_EPT (0x3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define AC_PINCTL_EPT_NATIVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define AC_PINCTL_EPT_HBR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define AC_PINCTL_VREFEN (0x7<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define AC_PINCTL_VREF_HIZ 0 /* Hi-Z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define AC_PINCTL_VREF_50 1 /* 50% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define AC_PINCTL_VREF_GRD 2 /* ground */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define AC_PINCTL_VREF_80 4 /* 80% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define AC_PINCTL_VREF_100 5 /* 100% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define AC_PINCTL_IN_EN (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define AC_PINCTL_OUT_EN (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define AC_PINCTL_HP_EN (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Pin sense - 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define AC_PINSENSE_IMPEDANCE_MASK (0x7fffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define AC_PINSENSE_PRESENCE (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define AC_PINSENSE_ELDV (1<<30) /* ELD valid (HDMI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* EAPD/BTL enable - 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define AC_EAPDBTL_BALANCED (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define AC_EAPDBTL_EAPD (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define AC_EAPDBTL_LR_SWAP (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* HDMI ELD data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define AC_ELDD_ELD_VALID (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define AC_ELDD_ELD_DATA 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* HDMI DIP size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define AC_DIPSIZE_ELD_BUF (1<<3) /* ELD buf size of packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define AC_DIPSIZE_PACK_IDX (0x07<<0) /* packet index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* HDMI DIP index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define AC_DIPIDX_PACK_IDX (0x07<<5) /* packet idnex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define AC_DIPIDX_BYTE_IDX (0x1f<<0) /* byte index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* HDMI DIP xmit (transmit) control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define AC_DIPXMIT_MASK (0x3<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define AC_DIPXMIT_DISABLE (0x0<<6) /* disable xmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define AC_DIPXMIT_ONCE (0x2<<6) /* xmit once then disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define AC_DIPXMIT_BEST (0x3<<6) /* best effort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* HDMI content protection (CP) control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define AC_CPCTRL_CES (1<<9) /* current encryption state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define AC_CPCTRL_READY (1<<8) /* ready bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define AC_CPCTRL_SUBTAG (0x1f<<3) /* subtag for unsol-resp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define AC_CPCTRL_STATE (3<<0) /* current CP request state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Converter channel <-> HDMI slot mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define AC_CVTMAP_HDMI_SLOT (0xf<<0) /* HDMI slot number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define AC_CVTMAP_CHAN (0xf<<4) /* converter channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* configuration default - 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define AC_DEFCFG_SEQUENCE (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define AC_DEFCFG_DEF_ASSOC (0xf<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define AC_DEFCFG_ASSOC_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define AC_DEFCFG_MISC (0xf<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define AC_DEFCFG_MISC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define AC_DEFCFG_MISC_NO_PRESENCE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define AC_DEFCFG_COLOR (0xf<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define AC_DEFCFG_COLOR_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define AC_DEFCFG_CONN_TYPE (0xf<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define AC_DEFCFG_CONN_TYPE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define AC_DEFCFG_DEVICE (0xf<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define AC_DEFCFG_DEVICE_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define AC_DEFCFG_LOCATION (0x3f<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define AC_DEFCFG_LOCATION_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define AC_DEFCFG_PORT_CONN (0x3<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define AC_DEFCFG_PORT_CONN_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Display pin's device list entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define AC_DE_PD (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define AC_DE_ELDV (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define AC_DE_IA (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* device device types (0x0-0xf) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) AC_JACK_LINE_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) AC_JACK_SPEAKER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) AC_JACK_HP_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) AC_JACK_CD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) AC_JACK_SPDIF_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) AC_JACK_DIG_OTHER_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) AC_JACK_MODEM_LINE_SIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) AC_JACK_MODEM_HAND_SIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) AC_JACK_LINE_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) AC_JACK_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) AC_JACK_MIC_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) AC_JACK_TELEPHONY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) AC_JACK_SPDIF_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) AC_JACK_DIG_OTHER_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) AC_JACK_OTHER = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* jack connection types (0x0-0xf) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) AC_JACK_CONN_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) AC_JACK_CONN_1_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) AC_JACK_CONN_1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) AC_JACK_CONN_ATAPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) AC_JACK_CONN_RCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) AC_JACK_CONN_OPTICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) AC_JACK_CONN_OTHER_DIGITAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) AC_JACK_CONN_OTHER_ANALOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) AC_JACK_CONN_DIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) AC_JACK_CONN_XLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) AC_JACK_CONN_RJ11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) AC_JACK_CONN_COMB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) AC_JACK_CONN_OTHER = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* jack colors (0x0-0xf) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) AC_JACK_COLOR_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) AC_JACK_COLOR_BLACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) AC_JACK_COLOR_GREY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) AC_JACK_COLOR_BLUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) AC_JACK_COLOR_GREEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) AC_JACK_COLOR_RED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) AC_JACK_COLOR_ORANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) AC_JACK_COLOR_YELLOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) AC_JACK_COLOR_PURPLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) AC_JACK_COLOR_PINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) AC_JACK_COLOR_WHITE = 0xe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) AC_JACK_COLOR_OTHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Jack location (0x0-0x3f) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* common case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) AC_JACK_LOC_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) AC_JACK_LOC_REAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) AC_JACK_LOC_FRONT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) AC_JACK_LOC_LEFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) AC_JACK_LOC_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) AC_JACK_LOC_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) AC_JACK_LOC_BOTTOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* bits 4-5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) AC_JACK_LOC_EXTERNAL = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) AC_JACK_LOC_INTERNAL = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) AC_JACK_LOC_SEPARATE = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) AC_JACK_LOC_OTHER = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* external on primary chasis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) AC_JACK_LOC_REAR_PANEL = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) AC_JACK_LOC_DRIVE_BAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) AC_JACK_LOC_RISER = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) AC_JACK_LOC_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) AC_JACK_LOC_ATAPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) AC_JACK_LOC_MOBILE_IN = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) AC_JACK_LOC_MOBILE_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Port connectivity (0-3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) AC_JACK_PORT_COMPLEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) AC_JACK_PORT_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) AC_JACK_PORT_FIXED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) AC_JACK_PORT_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* max. codec address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define HDA_MAX_CODEC_ADDRESS 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #endif /* __SOUND_HDA_VERBS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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