Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * HD-audio controller (Azalia) registers and helpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * For traditional reasons, we still use azx_ prefix here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __SOUND_HDA_REGISTER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __SOUND_HDA_REGISTER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <sound/hdaudio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define AZX_REG_GCAP			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define   AZX_GCAP_64OK		(1 << 0)   /* 64bit address support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define   AZX_GCAP_NSDO		(3 << 1)   /* # of serial data out signals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define   AZX_GCAP_BSS		(31 << 3)  /* # of bidirectional streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define   AZX_GCAP_ISS		(15 << 8)  /* # of input streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define   AZX_GCAP_OSS		(15 << 12) /* # of output streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AZX_REG_VMIN			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AZX_REG_VMAJ			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AZX_REG_OUTPAY			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AZX_REG_INPAY			0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AZX_REG_GCTL			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define   AZX_GCTL_RESET	(1 << 0)   /* controller reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define   AZX_GCTL_FCNTRL	(1 << 1)   /* flush control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define   AZX_GCTL_UNSOL	(1 << 8)   /* accept unsol. response enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AZX_REG_WAKEEN			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AZX_REG_STATESTS		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define AZX_REG_GSTS			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define   AZX_GSTS_FSTS		(1 << 1)   /* flush status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define AZX_REG_GCAP2			0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AZX_REG_LLCH			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define AZX_REG_OUTSTRMPAY		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AZX_REG_INSTRMPAY		0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AZX_REG_INTCTL			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AZX_REG_INTSTS			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AZX_REG_WALLCLK			0x30	/* 24Mhz source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AZX_REG_OLD_SSYNC		0x34	/* SSYNC for old ICH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AZX_REG_SSYNC			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AZX_REG_CORBLBASE		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define AZX_REG_CORBUBASE		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AZX_REG_CORBWP			0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define AZX_REG_CORBRP			0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define   AZX_CORBRP_RST	(1 << 15)  /* read pointer reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AZX_REG_CORBCTL			0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define   AZX_CORBCTL_RUN	(1 << 1)   /* enable DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define   AZX_CORBCTL_CMEIE	(1 << 0)   /* enable memory error irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AZX_REG_CORBSTS			0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define   AZX_CORBSTS_CMEI	(1 << 0)   /* memory error indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AZX_REG_CORBSIZE		0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AZX_REG_RIRBLBASE		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AZX_REG_RIRBUBASE		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AZX_REG_RIRBWP			0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define   AZX_RIRBWP_RST	(1 << 15)  /* write pointer reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AZX_REG_RINTCNT			0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AZX_REG_RIRBCTL			0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define   AZX_RBCTL_IRQ_EN	(1 << 0)   /* enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define   AZX_RBCTL_DMA_EN	(1 << 1)   /* enable DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define   AZX_RBCTL_OVERRUN_EN	(1 << 2)   /* enable overrun irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AZX_REG_RIRBSTS			0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define   AZX_RBSTS_IRQ		(1 << 0)   /* response irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define   AZX_RBSTS_OVERRUN	(1 << 2)   /* overrun irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AZX_REG_RIRBSIZE		0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define AZX_REG_IC			0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define AZX_REG_IR			0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AZX_REG_IRS			0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define   AZX_IRS_VALID		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define   AZX_IRS_BUSY		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define AZX_REG_DPLBASE			0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define AZX_REG_DPUBASE			0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define   AZX_DPLBASE_ENABLE	0x1	/* Enable position buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* stream register offsets from stream base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define AZX_REG_SD_CTL			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define AZX_REG_SD_CTL_3B		0x02 /* 3rd byte of SD_CTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define AZX_REG_SD_STS			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define AZX_REG_SD_LPIB			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define AZX_REG_SD_CBL			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define AZX_REG_SD_LVI			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define AZX_REG_SD_FIFOW		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define AZX_REG_SD_FIFOSIZE		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define AZX_REG_SD_FORMAT		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define AZX_REG_SD_FIFOL		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define AZX_REG_SD_BDLPL		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define AZX_REG_SD_BDLPU		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /* GTS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define AZX_REG_LLCH			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define AZX_REG_GTS_BASE		0x520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define AZX_REG_GTSCC	(AZX_REG_GTS_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AZX_REG_WALFCC	(AZX_REG_GTS_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AZX_REG_TSCCL	(AZX_REG_GTS_BASE + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AZX_REG_TSCCU	(AZX_REG_GTS_BASE + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AZX_REG_LLPFOC	(AZX_REG_GTS_BASE + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AZX_REG_LLPCL	(AZX_REG_GTS_BASE + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AZX_REG_LLPCU	(AZX_REG_GTS_BASE + 0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Haswell/Broadwell display HD-A controller Extended Mode registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AZX_REG_HSW_EM4			0x100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AZX_REG_HSW_EM5			0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Skylake/Broxton vendor-specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AZX_REG_VS_EM1			0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AZX_REG_VS_INRC			0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AZX_REG_VS_OUTRC		0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AZX_REG_VS_FIFOTRK		0x100C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AZX_REG_VS_FIFOTRK2		0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AZX_REG_VS_EM2			0x1030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AZX_REG_VS_EM3L			0x1038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AZX_REG_VS_EM3U			0x103C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AZX_REG_VS_EM4L			0x1040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AZX_REG_VS_EM4U			0x1044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AZX_REG_VS_LTRP			0x1048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AZX_REG_VS_D0I3C		0x104A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AZX_REG_VS_PCE			0x104B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AZX_REG_VS_L2MAGC		0x1050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AZX_REG_VS_L2LAHPT		0x1054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AZX_REG_VS_SDXDPIB_XBASE	0x1084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AZX_REG_VS_SDXDPIB_XINTERVAL	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AZX_REG_VS_SDXEFIFOS_XBASE	0x1094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AZX_REG_VS_SDXEFIFOS_XINTERVAL	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* PCI space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AZX_PCIREG_TCSEL		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * other constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* max number of fragments - we may use more if allocating more pages for BDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BDL_SIZE		4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AZX_MAX_FRAG		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* max buffer size - no h/w limit, you can increase as you like */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AZX_MAX_BUF_SIZE	(1024*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* RIRB int mask: overrun[2], response[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RIRB_INT_RESPONSE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RIRB_INT_OVERRUN	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RIRB_INT_MASK		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* STATESTS int mask: S3,SD2,SD1,SD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define STATESTS_INT_MASK	((1 << HDA_MAX_CODECS) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* SD_CTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SD_CTL_STREAM_RESET	0x01	/* stream reset bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SD_CTL_DMA_START	0x02	/* stream DMA start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SD_CTL_STRIPE		(3 << 16)	/* stripe control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SD_CTL_TRAFFIC_PRIO	(1 << 18)	/* traffic priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SD_CTL_DIR		(1 << 19)	/* bi-directional stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SD_CTL_STREAM_TAG_MASK	(0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SD_CTL_STREAM_TAG_SHIFT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* SD_CTL and SD_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SD_INT_DESC_ERR		0x10	/* descriptor error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SD_INT_FIFO_ERR		0x08	/* FIFO error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SD_INT_COMPLETE		0x04	/* completion interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SD_INT_MASK		(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				 SD_INT_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SD_CTL_STRIPE_MASK	0x3	/* stripe control mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* SD_STS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SD_STS_FIFO_READY	0x20	/* FIFO ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* INTCTL and INTSTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AZX_INT_ALL_STREAM	0xff	   /* all stream interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AZX_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AZX_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* below are so far hardcoded - should read registers in future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AZX_MAX_CORB_ENTRIES	256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AZX_MAX_RIRB_ENTRIES	256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Capability header  Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AZX_REG_CAP_HDR			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AZX_CAP_HDR_VER_OFF		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AZX_CAP_HDR_VER_MASK		(0xF << AZX_CAP_HDR_VER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AZX_CAP_HDR_ID_OFF		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AZX_CAP_HDR_ID_MASK		(0xFFF << AZX_CAP_HDR_ID_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AZX_CAP_HDR_NXT_PTR_MASK	0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* registers of Software Position Based FIFO Capability Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AZX_SPB_CAP_ID			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AZX_REG_SPB_BASE_ADDR		0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AZX_REG_SPB_SPBFCH		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AZX_REG_SPB_SPBFCCTL		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Base used to calculate the iterating register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AZX_SPB_BASE			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Interval used to calculate the iterating register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AZX_SPB_INTERVAL		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* SPIB base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AZX_SPB_SPIB			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* SPIB MAXFIFO base*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AZX_SPB_MAXFIFO			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* registers of Global Time Synchronization Capability Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AZX_GTS_CAP_ID			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AZX_REG_GTS_GTSCH		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AZX_REG_GTS_GTSCD		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AZX_REG_GTS_GTSCTLAC		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AZX_GTS_BASE			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AZX_GTS_INTERVAL		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* registers for Processing Pipe Capability Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AZX_PP_CAP_ID			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AZX_REG_PP_PPCH			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AZX_REG_PP_PPCTL		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AZX_PPCTL_PIE			(1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AZX_PPCTL_GPROCEN		(1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AZX_PPCTL_PROCEN(_X_)		(1<<(_X_))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AZX_REG_PP_PPSTS		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AZX_PPHC_BASE			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AZX_PPHC_INTERVAL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AZX_REG_PPHCLLPL		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AZX_REG_PPHCLLPU		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AZX_REG_PPHCLDPL		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AZX_REG_PPHCLDPU		0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AZX_PPLC_BASE			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AZX_PPLC_MULTI			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AZX_PPLC_INTERVAL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AZX_REG_PPLCCTL			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AZX_PPLCCTL_STRM_BITS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AZX_PPLCCTL_STRM_SHIFT		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AZX_REG_MASK(bit_num, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	(((1 << (bit_num)) - 1) << (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AZX_PPLCCTL_STRM_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AZX_PPLCCTL_RUN			(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AZX_PPLCCTL_STRST		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AZX_REG_PPLCFMT			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define AZX_REG_PPLCLLPL		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AZX_REG_PPLCLLPU		0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* registers for Multiple Links Capability Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AZX_ML_CAP_ID			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AZX_REG_ML_MLCH			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AZX_REG_ML_MLCD			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define AZX_ML_BASE			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AZX_ML_INTERVAL			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AZX_REG_ML_LCAP			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define AZX_REG_ML_LCTL			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define AZX_REG_ML_LOSIDV		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define AZX_REG_ML_LSDIID		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AZX_REG_ML_LPSOO		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define AZX_REG_ML_LPSIO		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AZX_REG_ML_LWALFC		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define AZX_REG_ML_LOUTPAY		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define AZX_REG_ML_LINPAY		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* bit0 is reserved, with BIT(1) mapping to stream1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ML_LOSIDV_STREAM_MASK		0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ML_LCTL_SCF_MASK			0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define AZX_MLCTL_SPA				(0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define AZX_MLCTL_CPA				(0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define AZX_MLCTL_SPA_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define AZX_MLCTL_CPA_SHIFT			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* registers for DMA Resume Capability Structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define AZX_DRSM_CAP_ID			0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define AZX_REG_DRSM_CTL		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Base used to calculate the iterating register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define AZX_DRSM_BASE			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Interval used to calculate the iterating register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define AZX_DRSM_INTERVAL		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Global time synchronization registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define GTSCC_TSCCD_MASK		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define GTSCC_TSCCD_SHIFT		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define GTSCC_TSCCI_MASK		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define GTSCC_CDMAS_DMA_DIR_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define WALFCC_CIF_MASK			0x1FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define WALFCC_FN_SHIFT			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define HDA_CLK_CYCLES_PER_FRAME	512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)  * An error occurs near frame "rollover". The clocks in frame value indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  * whether this error may have occurred. Here we use the value of 10. Please
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  * see the errata for the right number [<10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define HDA_MAX_CYCLE_VALUE		499
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HDA_MAX_CYCLE_OFFSET		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define HDA_MAX_CYCLE_READ_RETRY	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TSCCU_CCU_SHIFT			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define LLPC_CCU_SHIFT			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  * helpers to read the stream position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	return snd_hdac_stream_readl(stream, SD_LPIB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return le32_to_cpu(*stream->posbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #endif /* __SOUND_HDA_REGISTER_H */