^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SOUND_GUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SOUND_GUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Global structures used for GUS part of ALSA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/seq_midi_emul.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/seq_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* IO ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GUSP(gus, x) ((gus)->gf1.port + SNDRV_g_u_s_##x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SNDRV_g_u_s_MIDICTRL (0x320-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SNDRV_g_u_s_MIDISTAT (0x320-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SNDRV_g_u_s_MIDIDATA (0x321-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SNDRV_g_u_s_GF1PAGE (0x322-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SNDRV_g_u_s_GF1REGSEL (0x323-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SNDRV_g_u_s_GF1DATALOW (0x324-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SNDRV_g_u_s_GF1DATAHIGH (0x325-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SNDRV_g_u_s_IRQSTAT (0x226-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SNDRV_g_u_s_TIMERCNTRL (0x228-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SNDRV_g_u_s_TIMERDATA (0x229-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SNDRV_g_u_s_DRAM (0x327-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SNDRV_g_u_s_MIXCNTRLREG (0x220-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SNDRV_g_u_s_IRQDMACNTRLREG (0x22b-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SNDRV_g_u_s_REGCNTRLS (0x22f-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SNDRV_g_u_s_BOARDVERSION (0x726-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SNDRV_g_u_s_MIXCNTRLPORT (0x726-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SNDRV_g_u_s_IVER (0x325-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SNDRV_g_u_s_MIXDATAPORT (0x326-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SNDRV_g_u_s_MAXCNTRLPORT (0x326-0x220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* GF1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* global registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SNDRV_GF1_GB_ACTIVE_VOICES 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SNDRV_GF1_GB_VOICES_IRQ 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SNDRV_GF1_GB_GLOBAL_MODE 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SNDRV_GF1_GW_LFO_BASE 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SNDRV_GF1_GB_VOICES_IRQ_READ 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SNDRV_GF1_GB_DRAM_DMA_CONTROL 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SNDRV_GF1_GW_DRAM_DMA_LOW 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SNDRV_GF1_GW_DRAM_IO_LOW 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SNDRV_GF1_GB_DRAM_IO_HIGH 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SNDRV_GF1_GB_SOUND_BLASTER_CONTROL 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SNDRV_GF1_GB_ADLIB_TIMER_1 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SNDRV_GF1_GB_ADLIB_TIMER_2 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SNDRV_GF1_GB_RECORD_RATE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SNDRV_GF1_GB_REC_DMA_CONTROL 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SNDRV_GF1_GB_JOYSTICK_DAC_LEVEL 0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SNDRV_GF1_GB_RESET 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SNDRV_GF1_GB_DRAM_DMA_HIGH 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SNDRV_GF1_GW_DRAM_IO16 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SNDRV_GF1_GW_MEMORY_CONFIG 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SNDRV_GF1_GB_MEMORY_CONTROL 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SNDRV_GF1_GW_FIFO_RECORD_BASE_ADDR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SNDRV_GF1_GW_FIFO_PLAY_BASE_ADDR 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SNDRV_GF1_GW_FIFO_SIZE 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SNDRV_GF1_GW_INTERLEAVE 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SNDRV_GF1_GB_COMPATIBILITY 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SNDRV_GF1_GB_DECODE_CONTROL 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SNDRV_GF1_GB_VERSION_NUMBER 0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SNDRV_GF1_GB_MPU401_CONTROL_A 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SNDRV_GF1_GB_MPU401_CONTROL_B 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SNDRV_GF1_GB_EMULATION_IRQ 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* voice specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SNDRV_GF1_VB_ADDRESS_CONTROL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SNDRV_GF1_VW_FREQUENCY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SNDRV_GF1_VW_START_HIGH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SNDRV_GF1_VW_START_LOW 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SNDRV_GF1_VA_START SNDRV_GF1_VW_START_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SNDRV_GF1_VW_END_HIGH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SNDRV_GF1_VW_END_LOW 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SNDRV_GF1_VA_END SNDRV_GF1_VW_END_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SNDRV_GF1_VB_VOLUME_RATE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SNDRV_GF1_VB_VOLUME_START 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SNDRV_GF1_VB_VOLUME_END 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SNDRV_GF1_VW_VOLUME 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SNDRV_GF1_VW_CURRENT_HIGH 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SNDRV_GF1_VW_CURRENT_LOW 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SNDRV_GF1_VA_CURRENT SNDRV_GF1_VW_CURRENT_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SNDRV_GF1_VB_PAN 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SNDRV_GF1_VW_OFFSET_RIGHT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SNDRV_GF1_VB_VOLUME_CONTROL 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SNDRV_GF1_VB_UPPER_ADDRESS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SNDRV_GF1_VW_EFFECT_HIGH 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SNDRV_GF1_VW_EFFECT_LOW 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SNDRV_GF1_VA_EFFECT SNDRV_GF1_VW_EFFECT_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SNDRV_GF1_VW_OFFSET_LEFT 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SNDRV_GF1_VB_ACCUMULATOR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SNDRV_GF1_VB_MODE 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SNDRV_GF1_VW_EFFECT_VOLUME 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SNDRV_GF1_VB_FREQUENCY_LFO 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SNDRV_GF1_VB_VOLUME_LFO 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SNDRV_GF1_VW_OFFSET_RIGHT_FINAL 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SNDRV_GF1_VW_OFFSET_LEFT_FINAL 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SNDRV_GF1_VW_EFFECT_VOLUME_FINAL 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* ICS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SNDRV_ICS_MIC_DEV 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SNDRV_ICS_LINE_DEV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SNDRV_ICS_CD_DEV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SNDRV_ICS_GF1_DEV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SNDRV_ICS_NONE_DEV 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SNDRV_ICS_MASTER_DEV 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* LFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SNDRV_LFO_TREMOLO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SNDRV_LFO_VIBRATO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SNDRV_GF1_DMA_UNSIGNED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SNDRV_GF1_DMA_16BIT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SNDRV_GF1_DMA_IRQ 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SNDRV_GF1_DMA_WIDTH16 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SNDRV_GF1_DMA_READ 0x02 /* read from GUS's DRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SNDRV_GF1_DMA_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* ramp ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SNDRV_GF1_ATTEN(x) (snd_gf1_atten_table[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SNDRV_GF1_MIN_VOLUME 1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SNDRV_GF1_MAX_VOLUME 4095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SNDRV_GF1_MIN_OFFSET (SNDRV_GF1_MIN_VOLUME>>4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SNDRV_GF1_MAX_OFFSET 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SNDRV_GF1_MAX_TDEPTH 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* defines for memory manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SNDRV_GF1_MEM_BLOCK_16BIT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SNDRV_GF1_MEM_OWNER_DRIVER 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SNDRV_GF1_MEM_OWNER_WAVE_SIMPLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SNDRV_GF1_MEM_OWNER_WAVE_GF1 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SNDRV_GF1_MEM_OWNER_WAVE_IWFFFF 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* constants for interrupt handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SNDRV_GF1_HANDLER_MIDI_OUT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SNDRV_GF1_HANDLER_MIDI_IN 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SNDRV_GF1_HANDLER_TIMER1 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SNDRV_GF1_HANDLER_TIMER2 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SNDRV_GF1_HANDLER_VOICE 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SNDRV_GF1_HANDLER_DMA_WRITE 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SNDRV_GF1_HANDLER_DMA_READ 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SNDRV_GF1_HANDLER_ALL (0xffff0000&~SNDRV_GF1_HANDLER_VOICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* constants for DMA flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SNDRV_GF1_DMA_TRIGGER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct snd_gus_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* GF1 specific structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct snd_gf1_bank_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct snd_gf1_mem_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned short flags; /* flags - SNDRV_GF1_MEM_BLOCK_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned short owner; /* owner - SNDRV_GF1_MEM_OWNER_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int share; /* share count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int share_id[4]; /* share ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct snd_gf1_mem_block *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct snd_gf1_mem_block *prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct snd_gf1_mem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct snd_gf1_bank_info banks_8[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct snd_gf1_bank_info banks_16[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct snd_gf1_mem_block *first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct snd_gf1_mem_block *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct mutex memory_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct snd_gf1_dma_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void *buffer; /* buffer in computer's RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned long buf_addr; /* buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int addr; /* address in onboard memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int count; /* count in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int cmd; /* DMA command (format) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void (*ack)(struct snd_gus_card * gus, void *private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct snd_gf1_dma_block *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct snd_gus_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct snd_midi_channel_set * chset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct snd_gus_card * gus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int mode; /* operation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int client; /* sequencer client number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int port; /* sequencer port number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int midi_has_voices: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct snd_gus_voice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SNDRV_GF1_VOICE_TYPE_PCM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SNDRV_GF1_VOICE_TYPE_SYNTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SNDRV_GF1_VOICE_TYPE_MIDI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SNDRV_GF1_VFLG_RUNNING (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SNDRV_GF1_VFLG_EFFECT_TIMER1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SNDRV_GF1_VFLG_PAN (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) enum snd_gus_volume_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) VENV_BEFORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) VENV_ATTACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) VENV_SUSTAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) VENV_RELEASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) VENV_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) VENV_VOLUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct snd_gus_voice {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned int use: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pcm: 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) synth:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) midi: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned char client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned char port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned char index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned char pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int interrupt_stat_wave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int interrupt_stat_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void (*handler_wave) (struct snd_gus_card * gus, struct snd_gus_voice * voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void (*handler_volume) (struct snd_gus_card * gus, struct snd_gus_voice * voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void (*handler_effect) (struct snd_gus_card * gus, struct snd_gus_voice * voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void (*volume_change) (struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct snd_gus_sample_ops *sample_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* running status / registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned short fc_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned short fc_lfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned short gf1_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned char control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned char mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned char gf1_pan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned char effect_accumulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned char volume_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned char venv_value_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) enum snd_gus_volume_state venv_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) enum snd_gus_volume_state venv_state_prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned short vlo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned short vro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned short gf1_effect_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) void (*private_free)(struct snd_gus_voice *voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct snd_gf1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int enh_mode:1, /* enhanced mode (GFA1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) hw_lfo:1, /* use hardware LFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) sw_lfo:1, /* use software LFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) effect:1; /* use effect voices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long port; /* port of GF1 chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct resource *res_port1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct resource *res_port2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int irq; /* IRQ number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int dma1; /* DMA1 number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int dma2; /* DMA2 number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int memory; /* GUS's DRAM size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int rom_memory; /* GUS's ROM size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int rom_present; /* bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int rom_banks; /* GUS's ROM banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct snd_gf1_mem mem_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned short reg_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned short reg_regsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned short reg_data8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned short reg_data16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned short reg_irqstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned short reg_dram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned short reg_timerctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned short reg_timerdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned char ics_regs[6][2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned char active_voices; /* active voices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned char active_voice; /* selected voice (GF1PAGE register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct snd_gus_voice voices[32]; /* GF1 voices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int default_voice_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned short playback_freq; /* GF1 playback (mixing) frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned short mode; /* see to SNDRV_GF1_MODE_XXXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned char volume_ramp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned char smooth_pan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned char full_range_pan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned char pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned char *lfos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* interrupt handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) void (*interrupt_handler_midi_out) (struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void (*interrupt_handler_midi_in) (struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void (*interrupt_handler_timer1) (struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) void (*interrupt_handler_timer2) (struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) void (*interrupt_handler_dma_write) (struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void (*interrupt_handler_dma_read) (struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int interrupt_stat_midi_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int interrupt_stat_midi_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int interrupt_stat_timer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int interrupt_stat_timer2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int interrupt_stat_dma_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int interrupt_stat_dma_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int interrupt_stat_voice_lost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* synthesizer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int seq_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct snd_gus_port seq_ports[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned short timer_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct snd_timer *timer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct snd_timer *timer2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* midi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned short uart_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int uart_framing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned int uart_overrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* dma operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int dma_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int dma_shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct snd_gf1_dma_block *dma_data_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct snd_gf1_dma_block *dma_data_pcm_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct snd_gf1_dma_block *dma_data_synth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct snd_gf1_dma_block *dma_data_synth_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void (*dma_ack)(struct snd_gus_card * gus, void *private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void *dma_private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* pcm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int pcm_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int pcm_alloc_voices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned short pcm_volume_level_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned short pcm_volume_level_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned short pcm_volume_level_left1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned short pcm_volume_level_right1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned char pcm_rcntrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned char pad_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* main structure for GUS card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct snd_gus_card {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) initialized: 1, /* resources were initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) equal_irq:1, /* GF1 and CODEC shares IRQ (GUS MAX only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) equal_dma:1, /* if dma channels are equal (not valid for daughter board) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ics_flag:1, /* have we ICS mixer chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ics_flipped:1, /* ICS mixer have flipped some channels? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) codec_flag:1, /* have we CODEC chip? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) max_flag:1, /* have we GUS MAX card? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) max_ctrl_flag:1, /* have we original GUS MAX card? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) daughter_flag:1, /* have we daughter board? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) interwave:1, /* hey - we have InterWave card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ess_flag:1, /* ESS chip found... GUS Extreme */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ace_flag:1, /* GUS ACE detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) uart_enable:1; /* enable MIDI UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned short revision; /* revision of chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned short max_cntrl_val; /* GUS MAX control value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned short mix_cntrl_reg; /* mixer control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned short joystick_dac; /* joystick DAC level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int timer_dev; /* timer device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct snd_gf1 gf1; /* gf1 specific variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct snd_pcm_substream *pcm_cap_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int c_dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned int c_period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int c_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct snd_rawmidi *midi_uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct snd_rawmidi_substream *midi_substream_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct snd_rawmidi_substream *midi_substream_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) spinlock_t voice_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) spinlock_t active_voice_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) spinlock_t event_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) spinlock_t dma_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) spinlock_t pcm_volume_level_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) spinlock_t uart_cmd_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct mutex dma_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct mutex register_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* I/O functions for GF1/InterWave chip - gus_io.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static inline void snd_gf1_select_voice(struct snd_gus_card * gus, int voice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) spin_lock_irqsave(&gus->active_voice_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (voice != gus->gf1.active_voice) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) gus->gf1.active_voice = voice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) outb(voice, GUSP(gus, GF1PAGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) spin_unlock_irqrestore(&gus->active_voice_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static inline void snd_gf1_uart_cmd(struct snd_gus_card * gus, unsigned char b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) outb(gus->gf1.uart_cmd = b, GUSP(gus, MIDICTRL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static inline unsigned char snd_gf1_uart_stat(struct snd_gus_card * gus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return inb(GUSP(gus, MIDISTAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static inline void snd_gf1_uart_put(struct snd_gus_card * gus, unsigned char b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) outb(b, GUSP(gus, MIDIDATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static inline unsigned char snd_gf1_uart_get(struct snd_gus_card * gus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return inb(GUSP(gus, MIDIDATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) extern void snd_gf1_delay(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) extern void snd_gf1_ctrl_stop(struct snd_gus_card * gus, unsigned char reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) extern void snd_gf1_write8(struct snd_gus_card * gus, unsigned char reg, unsigned char data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) extern unsigned char snd_gf1_look8(struct snd_gus_card * gus, unsigned char reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static inline unsigned char snd_gf1_read8(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return snd_gf1_look8(gus, reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) extern void snd_gf1_write16(struct snd_gus_card * gus, unsigned char reg, unsigned int data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) extern unsigned short snd_gf1_look16(struct snd_gus_card * gus, unsigned char reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static inline unsigned short snd_gf1_read16(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return snd_gf1_look16(gus, reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) extern void snd_gf1_adlib_write(struct snd_gus_card * gus, unsigned char reg, unsigned char data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) extern void snd_gf1_dram_addr(struct snd_gus_card * gus, unsigned int addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) extern void snd_gf1_poke(struct snd_gus_card * gus, unsigned int addr, unsigned char data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) extern unsigned char snd_gf1_peek(struct snd_gus_card * gus, unsigned int addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) extern void snd_gf1_write_addr(struct snd_gus_card * gus, unsigned char reg, unsigned int addr, short w_16bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) extern unsigned int snd_gf1_read_addr(struct snd_gus_card * gus, unsigned char reg, short w_16bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) extern void snd_gf1_i_ctrl_stop(struct snd_gus_card * gus, unsigned char reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) extern void snd_gf1_i_write8(struct snd_gus_card * gus, unsigned char reg, unsigned char data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) extern unsigned char snd_gf1_i_look8(struct snd_gus_card * gus, unsigned char reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) extern void snd_gf1_i_write16(struct snd_gus_card * gus, unsigned char reg, unsigned int data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static inline unsigned char snd_gf1_i_read8(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return snd_gf1_i_look8(gus, reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) extern unsigned short snd_gf1_i_look16(struct snd_gus_card * gus, unsigned char reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static inline unsigned short snd_gf1_i_read16(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return snd_gf1_i_look16(gus, reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) extern void snd_gf1_select_active_voices(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* gus_lfo.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct _SND_IW_LFO_PROGRAM {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned short freq_and_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned char depth_final;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned char depth_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned short twave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned short depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) extern irqreturn_t snd_gf1_lfo_effect_interrupt(struct snd_gus_card * gus, snd_gf1_voice_t * voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) extern void snd_gf1_lfo_init(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) extern void snd_gf1_lfo_done(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) extern void snd_gf1_lfo_program(struct snd_gus_card * gus, int voice, int lfo_type, struct _SND_IW_LFO_PROGRAM *program);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) extern void snd_gf1_lfo_enable(struct snd_gus_card * gus, int voice, int lfo_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) extern void snd_gf1_lfo_disable(struct snd_gus_card * gus, int voice, int lfo_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) extern void snd_gf1_lfo_change_freq(struct snd_gus_card * gus, int voice, int lfo_type, int freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) extern void snd_gf1_lfo_change_depth(struct snd_gus_card * gus, int voice, int lfo_type, int depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) extern void snd_gf1_lfo_setup(struct snd_gus_card * gus, int voice, int lfo_type, int freq, int current_depth, int depth, int sweep, int shape);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) extern void snd_gf1_lfo_shutdown(struct snd_gus_card * gus, int voice, int lfo_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) extern void snd_gf1_lfo_command(struct snd_gus_card * gus, int voice, unsigned char *command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* gus_mem.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) void snd_gf1_mem_lock(struct snd_gf1_mem * alloc, int xup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int snd_gf1_mem_xfree(struct snd_gf1_mem * alloc, struct snd_gf1_mem_block * block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct snd_gf1_mem_block *snd_gf1_mem_alloc(struct snd_gf1_mem * alloc, int owner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) char *name, int size, int w_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int align, unsigned int *share_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int snd_gf1_mem_free(struct snd_gf1_mem * alloc, unsigned int address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int snd_gf1_mem_free_owner(struct snd_gf1_mem * alloc, int owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int snd_gf1_mem_init(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int snd_gf1_mem_done(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* gus_mem_proc.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int snd_gf1_mem_proc_init(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* gus_dma.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int snd_gf1_dma_init(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int snd_gf1_dma_done(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int snd_gf1_dma_transfer_block(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct snd_gf1_dma_block * block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int atomic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int synth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* gus_volume.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned short snd_gf1_lvol_to_gvol_raw(unsigned int vol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned short snd_gf1_translate_freq(struct snd_gus_card * gus, unsigned int freq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* gus_reset.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) void snd_gf1_set_default_handlers(struct snd_gus_card * gus, unsigned int what);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) void snd_gf1_smart_stop_voice(struct snd_gus_card * gus, unsigned short voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) void snd_gf1_stop_voice(struct snd_gus_card * gus, unsigned short voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) void snd_gf1_stop_voices(struct snd_gus_card * gus, unsigned short v_min, unsigned short v_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct snd_gus_voice *snd_gf1_alloc_voice(struct snd_gus_card * gus, int type, int client, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) void snd_gf1_free_voice(struct snd_gus_card * gus, struct snd_gus_voice *voice);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int snd_gf1_start(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int snd_gf1_stop(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* gus_mixer.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int snd_gf1_new_mixer(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* gus_pcm.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int snd_gf1_pcm_new(struct snd_gus_card *gus, int pcm_dev, int control_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) extern void snd_gf1_print_voice_registers(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* gus.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int snd_gus_use_inc(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) void snd_gus_use_dec(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int snd_gus_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int irq, int dma1, int dma2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int timer_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int voices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int pcm_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int effect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct snd_gus_card ** rgus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int snd_gus_initialize(struct snd_gus_card * gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* gus_irq.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) irqreturn_t snd_gus_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) void snd_gus_irq_profile_init(struct snd_gus_card *gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* gus_uart.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int snd_gf1_rawmidi_new(struct snd_gus_card *gus, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* gus_dram.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int snd_gus_dram_write(struct snd_gus_card *gus, char __user *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int addr, unsigned int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int snd_gus_dram_read(struct snd_gus_card *gus, char __user *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned int addr, unsigned int size, int rom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* gus_timer.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) void snd_gf1_timers_init(struct snd_gus_card *gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) void snd_gf1_timers_done(struct snd_gus_card *gus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #endif /* __SOUND_GUS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags