Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __SOUND_EMU8000_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __SOUND_EMU8000_REG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Register operations for the EMU8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (C) 1999 Steve Ratcliffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Based on awe_wave.c by Takashi Iwai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Data port addresses relative to the EMU base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define EMU8000_DATA0(e)    ((e)->port1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define EMU8000_DATA1(e)    ((e)->port2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define EMU8000_DATA2(e)    ((e)->port2+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define EMU8000_DATA3(e)    ((e)->port3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define EMU8000_PTR(e)      ((e)->port3+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Make a command from a register and channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define EMU8000_CMD(reg, chan) ((reg)<<5 | (chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Commands to read and write the EMU8000 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * These macros should be used for all register accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define EMU8000_CPF_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define EMU8000_PTRX_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define EMU8000_CVCF_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define EMU8000_VTFT_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define EMU8000_PSST_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define EMU8000_CSL_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(7, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define EMU8000_CCCA_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(0, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define EMU8000_HWCF4_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define EMU8000_HWCF5_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define EMU8000_HWCF6_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define EMU8000_SMALR_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define EMU8000_SMARR_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define EMU8000_SMALW_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define EMU8000_SMARW_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define EMU8000_SMLD_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define EMU8000_SMRD_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define EMU8000_WC_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define EMU8000_HWCF1_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define EMU8000_HWCF2_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define EMU8000_HWCF3_READ(emu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define EMU8000_INIT1_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(2, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define EMU8000_INIT2_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(2, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define EMU8000_INIT3_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(3, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define EMU8000_INIT4_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(3, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define EMU8000_ENVVOL_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(4, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define EMU8000_DCYSUSV_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(5, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define EMU8000_ENVVAL_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(6, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define EMU8000_DCYSUS_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(7, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define EMU8000_ATKHLDV_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(4, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define EMU8000_LFO1VAL_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(5, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define EMU8000_ATKHLD_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(6, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define EMU8000_LFO2VAL_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(7, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define EMU8000_IP_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(0, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define EMU8000_IFATN_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(1, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define EMU8000_PEFE_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(2, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define EMU8000_FMMOD_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(3, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define EMU8000_TREMFRQ_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(4, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EMU8000_FM2FRQ2_READ(emu, chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(5, (chan)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EMU8000_CPF_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EMU8000_PTRX_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define EMU8000_CVCF_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define EMU8000_VTFT_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EMU8000_PSST_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EMU8000_CSL_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(7, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EMU8000_CCCA_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(0, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EMU8000_HWCF4_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 9), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EMU8000_HWCF5_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 10), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EMU8000_HWCF6_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 13), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* this register is not documented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EMU8000_HWCF7_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 14), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EMU8000_SMALR_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 20), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EMU8000_SMARR_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 21), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EMU8000_SMALW_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 22), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EMU8000_SMARW_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 23), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EMU8000_SMLD_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 26), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EMU8000_SMRD_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 26), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EMU8000_WC_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 27), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EMU8000_HWCF1_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 29), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EMU8000_HWCF2_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 30), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EMU8000_HWCF3_WRITE(emu, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 31), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EMU8000_INIT1_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(2, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EMU8000_INIT2_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(2, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EMU8000_INIT3_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(3, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EMU8000_INIT4_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(3, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define EMU8000_ENVVOL_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(4, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EMU8000_DCYSUSV_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(5, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EMU8000_ENVVAL_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(6, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define EMU8000_DCYSUS_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(7, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EMU8000_ATKHLDV_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(4, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EMU8000_LFO1VAL_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(5, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EMU8000_ATKHLD_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(6, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EMU8000_LFO2VAL_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(7, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EMU8000_IP_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(0, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EMU8000_IFATN_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(1, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EMU8000_PEFE_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(2, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define EMU8000_FMMOD_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(3, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define EMU8000_TREMFRQ_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(4, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EMU8000_FM2FRQ2_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(5, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EMU8000_0080_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(4, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EMU8000_00A0_WRITE(emu, chan, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(5, (chan)), (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif /* __SOUND_EMU8000_REG_H */