^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SOUND_EMU8000_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SOUND_EMU8000_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Defines for the emu8000 (AWE32/64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999 Steve Ratcliffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1999-2000 Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/emux_synth.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/seq_kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Hardware parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EMU8000_MAX_DRAM (28 * 1024 * 1024) /* Max on-board mem is 28Mb ???*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EMU8000_DRAM_OFFSET 0x200000 /* Beginning of on board ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EMU8000_CHANNELS 32 /* Number of hardware channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EMU8000_DRAM_VOICES 30 /* number of normal voices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Flags to set a dma channel to read or write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EMU8000_RAM_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EMU8000_RAM_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EMU8000_RAM_CLOSE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EMU8000_RAM_MODE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EMU8000_RAM_RIGHT 0x10 /* use 'right' DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) EMU8000_CONTROL_BASS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) EMU8000_CONTROL_TREBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) EMU8000_CONTROL_CHORUS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) EMU8000_CONTROL_REVERB_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) EMU8000_CONTROL_FM_CHORUS_DEPTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) EMU8000_CONTROL_FM_REVERB_DEPTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) EMU8000_NUM_CONTROLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Structure to hold all state information for the emu8000 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Note 1: The chip supports 32 channels in hardware this is max_channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * some of the channels may be used for other things so max_channels is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * the number in use for wave voices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct snd_emu8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct snd_emux *emu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int index; /* sequencer client index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int seq_ports; /* number of sequencer ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int fm_chorus_depth; /* FM OPL3 chorus depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int fm_reverb_depth; /* FM OPL3 reverb depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int mem_size; /* memory size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long port1; /* Port usually base+0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long port2; /* Port usually at base+0x400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long port3; /* Port usually at base+0x800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct resource *res_port1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct resource *res_port2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct resource *res_port3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned short last_reg;/* Last register command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int dram_checked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct snd_card *card; /* The card that this belongs to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int chorus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int reverb_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int bass_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int treble_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct snd_util_memhdr *memhdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) spinlock_t control_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct snd_kcontrol *controls[EMU8000_NUM_CONTROLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct snd_pcm *pcm; /* pcm on emu8000 wavetable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* sequencer device id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SNDRV_SEQ_DEV_ID_EMU8000 "emu8000-synth"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* exported functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int snd_emu8000_new(struct snd_card *card, int device, long port, int seq_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct snd_seq_device **ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void snd_emu8000_poke(struct snd_emu8000 *emu, unsigned int port, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned short snd_emu8000_peek(struct snd_emu8000 *emu, unsigned int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void snd_emu8000_poke_dw(struct snd_emu8000 *emu, unsigned int port, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int snd_emu8000_peek_dw(struct snd_emu8000 *emu, unsigned int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void snd_emu8000_dma_chan(struct snd_emu8000 *emu, int ch, int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void snd_emu8000_init_fm(struct snd_emu8000 *emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void snd_emu8000_update_chorus_mode(struct snd_emu8000 *emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void snd_emu8000_update_reverb_mode(struct snd_emu8000 *emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void snd_emu8000_update_equalizer(struct snd_emu8000 *emu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int snd_emu8000_load_chorus_fx(struct snd_emu8000 *emu, int mode, const void __user *buf, long len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int snd_emu8000_load_reverb_fx(struct snd_emu8000 *emu, int mode, const void __user *buf, long len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif /* __SOUND_EMU8000_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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