Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __SOUND_DESIGNWARE_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __SOUND_DESIGNWARE_I2S_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * struct i2s_clk_config_data - represent i2s clk configuration data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * @chan_nr: number of channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * @data_width: number of bits per sample (8/16/24/32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct i2s_clk_config_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	int chan_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	u32 data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	u32 sample_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct i2s_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	#define DWC_I2S_PLAY	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	#define DWC_I2S_RECORD	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	#define DW_I2S_SLAVE	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	#define DW_I2S_MASTER	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	unsigned int cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	u32 snd_fmts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	u32 snd_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	#define DW_I2S_QUIRK_COMP_REG_OFFSET	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	#define DW_I2S_QUIRK_COMP_PARAM1	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	#define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	unsigned int i2s_reg_comp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	unsigned int i2s_reg_comp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	void *play_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	void *capture_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	bool (*filter)(struct dma_chan *chan, void *slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct i2s_dma_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u32 max_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	enum dma_slave_buswidth addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	bool (*filter)(struct dma_chan *chan, void *slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* I2S DMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2S_RXDMA		0x01C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2S_TXDMA		0x01C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TWO_CHANNEL_SUPPORT	2	/* up to 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FOUR_CHANNEL_SUPPORT	4	/* up to 3.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SIX_CHANNEL_SUPPORT	6	/* up to 5.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EIGHT_CHANNEL_SUPPORT	8	/* up to 7.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif /*  __SOUND_DESIGNWARE_I2S_H */