Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __SOUND_CS8427_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __SOUND_CS8427_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Routines for Cirrus Logic CS8427
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <sound/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CS8427_BASE_ADDR	0x10	/* base I2C address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CS8427_REG_AUTOINC	0x80	/* flag - autoincrement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CS8427_REG_CONTROL1	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CS8427_REG_CONTROL2	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CS8427_REG_DATAFLOW	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CS8427_REG_CLOCKSOURCE	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CS8427_REG_SERIALINPUT	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CS8427_REG_SERIALOUTPUT	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CS8427_REG_INT1STATUS	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CS8427_REG_INT2STATUS	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CS8427_REG_INT1MASK	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CS8427_REG_INT1MODEMSB	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CS8427_REG_INT1MODELSB	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CS8427_REG_INT2MASK	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CS8427_REG_INT2MODEMSB	0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CS8427_REG_INT2MODELSB	0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CS8427_REG_RECVCSDATA	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CS8427_REG_RECVERRORS	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CS8427_REG_RECVERRMASK	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CS8427_REG_CSDATABUF	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CS8427_REG_UDATABUF	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CS8427_REG_QSUBCODE	0x14	/* 0x14-0x1d (10 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CS8427_REG_OMCKRMCKRATIO 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CS8427_REG_CORU_DATABUF	0x20	/* 24 byte buffer area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CS8427_REG_ID_AND_VER	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* CS8427_REG_CONTROL1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CS8427_SWCLK		(1<<7)	/* 0 = RMCK default, 1 = OMCK output on RMCK pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CS8427_VSET		(1<<6)	/* 0 = valid PCM data, 1 = invalid PCM data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CS8427_MUTESAO		(1<<5)	/* mute control for the serial audio output port, 0 = disabled, 1 = enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CS8427_MUTEAES		(1<<4)	/* mute control for the AES transmitter output, 0 = disabled, 1 = enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CS8427_INTMASK		(3<<1)	/* interrupt output pin setup mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CS8427_INTACTHIGH	(0<<1)	/* active high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CS8427_INTACTLOW	(1<<1)	/* active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CS8427_INTOPENDRAIN	(2<<1)	/* open drain, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CS8427_TCBLDIR		(1<<0)	/* 0 = TCBL is an input, 1 = TCBL is an output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* CS8427_REQ_CONTROL2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CS8427_HOLDMASK		(3<<5)	/* action when a receiver error occurs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CS8427_HOLDLASTSAMPLE	(0<<5)	/* hold the last valid sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CS8427_HOLDZERO		(1<<5)	/* replace the current audio sample with zero (mute) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CS8427_HOLDNOCHANGE	(2<<5)	/* do not change the received audio sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CS8427_RMCKF		(1<<4)	/* 0 = 256*Fsi, 1 = 128*Fsi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CS8427_MMR		(1<<3)	/* AES3 receiver operation, 0 = stereo, 1 = mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CS8427_MMT		(1<<2)	/* AES3 transmitter operation, 0 = stereo, 1 = mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CS8427_MMTCS		(1<<1)	/* 0 = use A + B CS data, 1 = use MMTLR CS data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CS8427_MMTLR		(1<<0)	/* 0 = use A CS data, 1 = use B CS data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* CS8427_REG_DATAFLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CS8427_TXOFF		(1<<6)	/* AES3 transmitter Output, 0 = normal operation, 1 = off (0V) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CS8427_AESBP		(1<<5)	/* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CS8427_TXDMASK		(3<<3)	/* AES3 Transmitter Data Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CS8427_TXDSERIAL	(1<<3)	/* TXD - serial audio input port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CS8427_TXAES3DRECEIVER	(2<<3)	/* TXD - AES3 receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CS8427_SPDMASK		(3<<1)	/* Serial Audio Output Port Data Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CS8427_SPDSERIAL	(1<<1)	/* SPD - serial audio input port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CS8427_SPDAES3RECEIVER	(2<<1)	/* SPD - AES3 receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* CS8427_REG_CLOCKSOURCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CS8427_RUN		(1<<6)	/* 0 = clock off, 1 = clock on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CS8427_CLKMASK		(3<<4)	/* OMCK frequency mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CS8427_CLK256		(0<<4)	/* 256*Fso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CS8427_CLK384		(1<<4)	/* 384*Fso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CS8427_CLK512		(2<<4)	/* 512*Fso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CS8427_OUTC		(1<<3)	/* Output Time Base, 0 = OMCK, 1 = recovered input clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CS8427_INC		(1<<2)	/* Input Time Base Clock Source, 0 = recoverd input clock, 1 = OMCK input pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CS8427_RXDMASK		(3<<0)	/* Recovered Input Clock Source Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CS8427_RXDILRCK		(0<<0)	/* 256*Fsi from ILRCK pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CS8427_RXDAES3INPUT	(1<<0)	/* 256*Fsi from AES3 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CS8427_EXTCLOCKRESET	(2<<0)	/* bypass PLL, 256*Fsi clock, synchronous reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CS8427_EXTCLOCK		(3<<0)	/* bypass PLL, 256*Fsi clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* CS8427_REG_SERIALINPUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CS8427_SIMS		(1<<7)	/* 0 = slave, 1 = master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CS8427_SISF		(1<<6)	/* ISCLK freq, 0 = 64*Fsi, 1 = 128*Fsi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CS8427_SIRESMASK	(3<<4)	/* Resolution of the input data for right justified formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CS8427_SIRES24		(0<<4)	/* SIRES 24-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CS8427_SIRES20		(1<<4)	/* SIRES 20-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CS8427_SIRES16		(2<<4)	/* SIRES 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CS8427_SIJUST		(1<<3)	/* Justification of SDIN data relative to ILRCK, 0 = left-justified, 1 = right-justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CS8427_SIDEL		(1<<2)	/* Delay of SDIN data relative to ILRCK for left-justified data formats, 0 = first ISCLK period, 1 = second ISCLK period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CS8427_SISPOL		(1<<1)	/* ICLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CS8427_SILRPOL		(1<<0)	/* ILRCK clock polarity, 0 = SDIN data left channel when ILRCK is high, 1 = SDIN right when ILRCK is high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* CS8427_REG_SERIALOUTPUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CS8427_SOMS		(1<<7)	/* 0 = slave, 1 = master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CS8427_SOSF		(1<<6)	/* OSCLK freq, 0 = 64*Fso, 1 = 128*Fso */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CS8427_SORESMASK	(3<<4)	/* Resolution of the output data on SDOUT and AES3 output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CS8427_SORES24		(0<<4)	/* SIRES 24-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CS8427_SORES20		(1<<4)	/* SIRES 20-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CS8427_SORES16		(2<<4)	/* SIRES 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CS8427_SORESDIRECT	(2<<4)	/* SIRES direct copy from AES3 receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CS8427_SOJUST		(1<<3)	/* Justification of SDOUT data relative to OLRCK, 0 = left-justified, 1 = right-justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CS8427_SODEL		(1<<2)	/* Delay of SDOUT data relative to OLRCK for left-justified data formats, 0 = first OSCLK period, 1 = second OSCLK period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CS8427_SOSPOL		(1<<1)	/* OSCLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CS8427_SOLRPOL		(1<<0)	/* OLRCK clock polarity, 0 = SDOUT data left channel when OLRCK is high, 1 = SDOUT right when OLRCK is high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* CS8427_REG_INT1STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CS8427_TSLIP		(1<<7)	/* AES3 transmitter source data slip interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CS8427_OSLIP		(1<<6)	/* Serial audio output port data slip interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CS8427_DETC		(1<<2)	/* D to E C-buffer transfer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CS8427_EFTC		(1<<1)	/* E to F C-buffer transfer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CS8427_RERR		(1<<0)	/* A receiver error has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* CS8427_REG_INT2STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CS8427_DETU		(1<<3)	/* D to E U-buffer transfer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CS8427_EFTU		(1<<2)	/* E to F U-buffer transfer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CS8427_QCH		(1<<1)	/* A new block of Q-subcode data is available for reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* CS8427_REG_INT1MODEMSB && CS8427_REG_INT1MODELSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* bits are defined in CS8427_REG_INT1STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* CS8427_REG_INT2MODEMSB && CS8427_REG_INT2MODELSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* bits are defined in CS8427_REG_INT2STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CS8427_INTMODERISINGMSB	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CS8427_INTMODERESINGLSB	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CS8427_INTMODEFALLINGMSB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CS8427_INTMODEFALLINGLSB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CS8427_INTMODELEVELMSB	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CS8427_INTMODELEVELLSB	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* CS8427_REG_RECVCSDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CS8427_AUXMASK		(15<<4)	/* auxiliary data field width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CS8427_AUXSHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CS8427_PRO		(1<<3)	/* Channel status block format indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CS8427_AUDIO		(1<<2)	/* Audio indicator (0 = audio, 1 = nonaudio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CS8427_COPY		(1<<1)	/* 0 = copyright asserted, 1 = copyright not asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CS8427_ORIG		(1<<0)	/* SCMS generation indicator, 0 = 1st generation or highter, 1 = original */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* CS8427_REG_RECVERRORS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* CS8427_REG_RECVERRMASK for CS8427_RERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CS8427_QCRC		(1<<6)	/* Q-subcode data CRC error indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CS8427_CCRC		(1<<5)	/* Chancnel Status Block Cyclick Redundancy Check Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CS8427_UNLOCK		(1<<4)	/* PLL lock status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CS8427_V		(1<<3)	/* 0 = valid data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CS8427_CONF		(1<<2)	/* Confidence bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CS8427_BIP		(1<<1)	/* Bi-phase error bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CS8427_PAR		(1<<0)	/* Parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* CS8427_REG_CSDATABUF	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CS8427_BSEL		(1<<5)	/* 0 = CS data, 1 = U data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CS8427_CBMR		(1<<4)	/* 0 = overwrite first 5 bytes for CS D to E buffer, 1 = prevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CS8427_DETCI		(1<<3)	/* D to E CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CS8427_EFTCI		(1<<2)	/* E to F CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CS8427_CAM		(1<<1)	/* CS data buffer control port access mode bit, 0 = one byte, 1 = two byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CS8427_CHS		(1<<0)	/* Channel select bit, 0 = Channel A, 1 = Channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* CS8427_REG_UDATABUF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CS8427_UD		(1<<4)	/* User data pin (U) direction, 0 = input, 1 = output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CS8427_UBMMASK		(3<<2)	/* Operating mode of the AES3 U bit manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CS8427_UBMZEROS		(0<<2)	/* transmit all zeros mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CS8427_UBMBLOCK		(1<<2)	/* block mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CS8427_DETUI		(1<<1)	/* D to E U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CS8427_EFTUI		(1<<1)	/* E to F U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* CS8427_REG_ID_AND_VER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CS8427_IDMASK		(15<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CS8427_IDSHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CS8427_VERMASK		(15<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CS8427_VERSHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CS8427_VER8427A		0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct snd_pcm_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int snd_cs8427_init(struct snd_i2c_bus *bus, struct snd_i2c_device *device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int snd_cs8427_create(struct snd_i2c_bus *bus, unsigned char addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		      unsigned int reset_timeout, struct snd_i2c_device **r_cs8427);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int snd_cs8427_reg_write(struct snd_i2c_device *device, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			 unsigned char val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int snd_cs8427_iec958_build(struct snd_i2c_device *cs8427,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			    struct snd_pcm_substream *playback_substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			    struct snd_pcm_substream *capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int snd_cs8427_iec958_active(struct snd_i2c_device *cs8427, int active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int snd_cs8427_iec958_pcm(struct snd_i2c_device *cs8427, unsigned int rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif /* __SOUND_CS8427_H */