Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Definitions for CS4271 ASoC codec driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __CS4271_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __CS4271_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct cs4271_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	int gpio_nreset;	/* GPIO driving Reset pin, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	bool amutec_eq_bmutec;	/* flag to enable AMUTEC=BMUTEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	 * The CS4271 requires its LRCLK and MCLK to be stable before its RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	 * line is de-asserted. That also means that clocks cannot be changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	 * without putting the chip back into hardware reset, which also requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	 * a complete re-initialization of all registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	 * One (undocumented) workaround is to assert and de-assert the PDN bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	 * in the MODE2 register. This workaround can be enabled with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	 * following flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	 * Note that this is not needed in case the clocks are stable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	 * throughout the entire runtime of the codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	bool enable_soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif /* __CS4271_H */