Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __SOUND_CS4231_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __SOUND_CS4231_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Definitions for CS4231 & InterWave chips & compatible chips registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* IO ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CS4231P(x)		(c_d_c_CS4231##x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define c_d_c_CS4231REGSEL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define c_d_c_CS4231REG		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define c_d_c_CS4231STATUS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define c_d_c_CS4231PIO		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* codec registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CS4231_LEFT_INPUT	0x00	/* left input control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CS4231_RIGHT_INPUT	0x01	/* right input control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CS4231_AUX1_LEFT_INPUT	0x02	/* left AUX1 input control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CS4231_AUX1_RIGHT_INPUT	0x03	/* right AUX1 input control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CS4231_AUX2_LEFT_INPUT	0x04	/* left AUX2 input control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CS4231_AUX2_RIGHT_INPUT	0x05	/* right AUX2 input control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CS4231_LEFT_OUTPUT	0x06	/* left output control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CS4231_RIGHT_OUTPUT	0x07	/* right output control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CS4231_PLAYBK_FORMAT	0x08	/* clock and data format - playback - bits 7-0 MCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CS4231_IFACE_CTRL	0x09	/* interface control - bits 7-2 MCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CS4231_PIN_CTRL		0x0a	/* pin control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CS4231_TEST_INIT	0x0b	/* test and initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CS4231_MISC_INFO	0x0c	/* miscellaneous information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CS4231_LOOPBACK		0x0d	/* loopback control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CS4231_PLY_UPR_CNT	0x0e	/* playback upper base count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CS4231_PLY_LWR_CNT	0x0f	/* playback lower base count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CS4231_ALT_FEATURE_1	0x10	/* alternate #1 feature enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define AD1845_AF1_MIC_LEFT	0x10	/* alternate #1 feature + MIC left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CS4231_ALT_FEATURE_2	0x11	/* alternate #2 feature enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AD1845_AF2_MIC_RIGHT	0x11	/* alternate #2 feature + MIC right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CS4231_LEFT_LINE_IN	0x12	/* left line input control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CS4231_RIGHT_LINE_IN	0x13	/* right line input control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CS4231_TIMER_LOW	0x14	/* timer low byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CS4231_TIMER_HIGH	0x15	/* timer high byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CS4231_LEFT_MIC_INPUT	0x16	/* left MIC input control register (InterWave only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define AD1845_UPR_FREQ_SEL	0x16	/* upper byte of frequency select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CS4231_RIGHT_MIC_INPUT	0x17	/* right MIC input control register (InterWave only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define AD1845_LWR_FREQ_SEL	0x17	/* lower byte of frequency select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CS4236_EXT_REG		0x17	/* extended register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CS4231_IRQ_STATUS	0x18	/* irq status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CS4231_LINE_LEFT_OUTPUT	0x19	/* left line output control register (InterWave only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CS4231_VERSION		0x19	/* CS4231(A) - version values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CS4231_MONO_CTRL	0x1a	/* mono input/output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CS4231_LINE_RIGHT_OUTPUT 0x1b	/* right line output control register (InterWave only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AD1845_PWR_DOWN		0x1b	/* power down control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CS4235_LEFT_MASTER	0x1b	/* left master output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CS4231_REC_FORMAT	0x1c	/* clock and data format - record - bits 7-0 MCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AD1845_CLOCK		0x1d	/* crystal clock select and total power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CS4235_RIGHT_MASTER	0x1d	/* right master output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CS4231_REC_UPR_CNT	0x1e	/* record upper count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CS4231_REC_LWR_CNT	0x1f	/* record lower count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* definitions for codec register select port - CODECP( REGSEL ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CS4231_INIT		0x80	/* CODEC is initializing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CS4231_MCE		0x40	/* mode change enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CS4231_TRD		0x20	/* transfer request disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* definitions for codec status register - CODECP( STATUS ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CS4231_GLOBALIRQ	0x01	/* IRQ is active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* definitions for codec irq status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CS4231_PLAYBACK_IRQ	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CS4231_RECORD_IRQ	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CS4231_TIMER_IRQ	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CS4231_ALL_IRQS		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CS4231_REC_UNDERRUN	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CS4231_REC_OVERRUN	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CS4231_PLY_OVERRUN	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CS4231_PLY_UNDERRUN	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CS4231_ENABLE_MIC_GAIN	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CS4231_MIXS_LINE	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CS4231_MIXS_AUX1	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CS4231_MIXS_MIC		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CS4231_MIXS_ALL		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CS4231_LINEAR_8		0x00	/* 8-bit unsigned data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CS4231_ALAW_8		0x60	/* 8-bit A-law companded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CS4231_ULAW_8		0x20	/* 8-bit U-law companded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CS4231_LINEAR_16	0x40	/* 16-bit twos complement data - little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CS4231_LINEAR_16_BIG	0xc0	/* 16-bit twos complement data - big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CS4231_ADPCM_16		0xa0	/* 16-bit ADPCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CS4231_STEREO		0x10	/* stereo mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* bits 3-1 define frequency divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CS4231_XTAL1		0x00	/* 24.576 crystal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CS4231_XTAL2		0x01	/* 16.9344 crystal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* definitions for interface control register - CS4231_IFACE_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CS4231_RECORD_PIO	0x80	/* record PIO enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CS4231_PLAYBACK_PIO	0x40	/* playback PIO enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CS4231_CALIB_MODE	0x18	/* calibration mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CS4231_AUTOCALIB	0x08	/* auto calibrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CS4231_SINGLE_DMA	0x04	/* use single DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CS4231_RECORD_ENABLE	0x02	/* record enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CS4231_PLAYBACK_ENABLE	0x01	/* playback enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* definitions for pin control register - CS4231_PIN_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CS4231_IRQ_ENABLE	0x02	/* enable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CS4231_XCTL1		0x40	/* external control #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CS4231_XCTL0		0x80	/* external control #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* definitions for test and init register - CS4231_TEST_INIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CS4231_CALIB_IN_PROGRESS 0x20	/* auto calibrate in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CS4231_DMA_REQUEST	0x10	/* DMA request in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* definitions for misc control register - CS4231_MISC_INFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CS4231_MODE2		0x40	/* MODE 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CS4231_IW_MODE3		0x6c	/* MODE 3 - InterWave enhanced mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CS4231_4236_MODE3	0xe0	/* MODE 3 - CS4236+ enhanced mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define	CS4231_DACZ		0x01	/* zero DAC when underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CS4231_TIMER_ENABLE	0x40	/* codec timer enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CS4231_OLB		0x80	/* output level bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* definitions for Extended Registers - CS4236+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CS4236_REG(i23val)	(((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CS4236_I23VAL(reg)	((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CS4236_LEFT_LINE	0x08	/* left LINE alternate volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CS4236_RIGHT_LINE	0x18	/* right LINE alternate volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CS4236_LEFT_MIC		0x28	/* left MIC volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CS4236_RIGHT_MIC	0x38	/* right MIC volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CS4236_LEFT_MIX_CTRL	0x48	/* synthesis and left input mixer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CS4236_RIGHT_MIX_CTRL	0x58	/* right input mixer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CS4236_LEFT_FM		0x68	/* left FM volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CS4236_RIGHT_FM		0x78	/* right FM volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CS4236_LEFT_DSP		0x88	/* left DSP serial port volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CS4236_RIGHT_DSP	0x98	/* right DSP serial port volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CS4236_RIGHT_LOOPBACK	0xa8	/* right loopback monitor volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CS4236_DAC_MUTE		0xb8	/* DAC mute and IFSE enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CS4236_ADC_RATE		0xc8	/* indenpendent ADC sample frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CS4236_DAC_RATE		0xd8	/* indenpendent DAC sample frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CS4236_LEFT_MASTER	0xe8	/* left master digital audio volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CS4236_RIGHT_MASTER	0xf8	/* right master digital audio volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CS4236_LEFT_WAVE	0x0c	/* left wavetable serial port volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CS4236_RIGHT_WAVE	0x1c	/* right wavetable serial port volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CS4236_VERSION		0x9c	/* chip version and ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* definitions for extended registers - OPTI93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OPTi931_AUX_LEFT_INPUT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OPTi931_AUX_RIGHT_INPUT	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OPTi93X_MIC_LEFT_INPUT	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OPTi93X_MIC_RIGHT_INPUT	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OPTi93X_OUT_LEFT	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OPTi93X_OUT_RIGHT	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif /* __SOUND_CS4231_REGS_H */