^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SOUND_AK4117_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SOUND_AK4117_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Routines for Asahi Kasei AK4117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define AK4117_REG_PWRDN 0x00 /* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AK4117_REG_CLOCK 0x01 /* clock control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AK4117_REG_IO 0x02 /* input/output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AK4117_REG_INT0_MASK 0x03 /* interrupt0 mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AK4117_REG_INT1_MASK 0x04 /* interrupt1 mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AK4117_REG_RCS0 0x05 /* receiver status 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AK4117_REG_RCS1 0x06 /* receiver status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AK4117_REG_RCS2 0x07 /* receiver status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AK4117_REG_RXCSB0 0x08 /* RX channel status byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AK4117_REG_RXCSB1 0x09 /* RX channel status byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AK4117_REG_RXCSB2 0x0a /* RX channel status byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AK4117_REG_RXCSB3 0x0b /* RX channel status byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AK4117_REG_RXCSB4 0x0c /* RX channel status byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AK4117_REG_Pc0 0x0d /* burst preamble Pc byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AK4117_REG_Pc1 0x0e /* burst preamble Pc byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AK4117_REG_Pd0 0x0f /* burst preamble Pd byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AK4117_REG_Pd1 0x10 /* burst preamble Pd byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AK4117_REG_QSUB_ABSFRM 0x1a /* Q-subcode absolute frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AK4117_REG_RXCSB_SIZE ((AK4117_REG_RXCSB4-AK4117_REG_RXCSB0)+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AK4117_REG_QSUB_SIZE ((AK4117_REG_QSUB_ABSFRM-AK4117_REG_QSUB_ADDR)+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* AK4117_REG_PWRDN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AK4117_EXCT (1<<4) /* 0 = X'tal mode, 1 = external clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AK4117_XTL1 (1<<3) /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AK4117_XTL0 (1<<2) /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AK4117_XTL_11_2896M (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AK4117_XTL_12_288M AK4117_XTL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AK4117_XTL_24_576M AK4117_XTL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AK4117_XTL_EXT (AK4117_XTL1|AK4117_XTL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AK4117_PWN (1<<1) /* 0 = power down, 1 = normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AK4117_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* AK4117_REQ_CLOCK bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AK4117_LP (1<<7) /* 0 = normal mode, 1 = low power mode (Fs up to 48kHz only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AK4117_PKCS1 (1<<6) /* master clock frequency at PLL mode (when LP == 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AK4117_PKCS0 (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AK4117_PKCS_512fs (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AK4117_PKCS_256fs AK4117_PKCS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AK4117_PKCS_128fs AK4117_PKCS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AK4117_DIV (1<<4) /* 0 = MCKO == Fs, 1 = MCKO == Fs / 2; X'tal mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AK4117_XCKS1 (1<<3) /* master clock frequency at X'tal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AK4117_XCKS0 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AK4117_XCKS_128fs (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AK4117_XCKS_256fs AK4117_XCKS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AK4117_XCKS_512fs AK4117_XCKS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AK4117_XCKS_1024fs (AK4117_XCKS1|AK4117_XCKS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AK4117_CM1 (1<<1) /* MCKO operation mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AK4117_CM0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AK4117_CM_PLL (0) /* use RX input as master clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AK4117_CM_XTAL (AK4117_CM0) /* use X'tal as master clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AK4117_CM_PLL_XTAL (AK4117_CM1) /* use Rx input but X'tal when PLL loses lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AK4117_CM_MONITOR (AK4117_CM0|AK4117_CM1) /* use X'tal as master clock, but use PLL for monitoring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* AK4117_REG_IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AK4117_IPS (1<<7) /* Input Recovery Data Select, 0 = RX0, 1 = RX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AK4117_UOUTE (1<<6) /* U-bit output enable to UOUT, 0 = disable, 1 = enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AK4117_CS12 (1<<5) /* channel status select, 0 = channel1, 1 = channel2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AK4117_EFH2 (1<<4) /* INT0 pin hold count select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AK4117_EFH1 (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AK4117_EFH_512LRCLK (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AK4117_EFH_1024LRCLK (AK4117_EFH1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AK4117_EFH_2048LRCLK (AK4117_EFH2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AK4117_EFH_4096LRCLK (AK4117_EFH1|AK4117_EFH2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AK4117_DIF2 (1<<2) /* audio data format control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AK4117_DIF1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AK4117_DIF0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AK4117_DIF_16R (0) /* STDO: 16-bit, right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AK4117_DIF_18R (AK4117_DIF0) /* STDO: 18-bit, right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AK4117_DIF_20R (AK4117_DIF1) /* STDO: 20-bit, right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AK4117_DIF_24R (AK4117_DIF1|AK4117_DIF0) /* STDO: 24-bit, right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AK4117_DIF_24L (AK4117_DIF2) /* STDO: 24-bit, left justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AK4117_DIF_24I2S (AK4117_DIF2|AK4117_DIF0) /* STDO: I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* AK4117_REG_INT0_MASK & AK4117_REG_INT1_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AK4117_MULK (1<<7) /* mask enable for UNLOCK bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AK4117_MPAR (1<<6) /* mask enable for PAR bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AK4117_MAUTO (1<<5) /* mask enable for AUTO bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AK4117_MV (1<<4) /* mask enable for V bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AK4117_MAUD (1<<3) /* mask enable for AUDION bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AK4117_MSTC (1<<2) /* mask enable for STC bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AK4117_MCIT (1<<1) /* mask enable for CINT bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AK4117_MQIT (1<<0) /* mask enable for QINT bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* AK4117_REG_RCS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AK4117_UNLCK (1<<7) /* PLL lock status, 0 = lock, 1 = unlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AK4117_PAR (1<<6) /* parity error or biphase error status, 0 = no error, 1 = error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AK4117_AUTO (1<<5) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AK4117_V (1<<4) /* Validity bit, 0 = valid, 1 = invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AK4117_AUDION (1<<3) /* audio bit output, 0 = audio, 1 = non-audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AK4117_STC (1<<2) /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AK4117_CINT (1<<1) /* channel status buffer interrupt, 0 = no change, 1 = change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AK4117_QINT (1<<0) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* AK4117_REG_RCS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AK4117_DTSCD (1<<6) /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AK4117_NPCM (1<<5) /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AK4117_PEM (1<<4) /* Pre-emphasis detect, 0 = OFF, 1 = ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AK4117_FS3 (1<<3) /* sampling frequency detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AK4117_FS2 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AK4117_FS1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AK4117_FS0 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AK4117_FS_44100HZ (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AK4117_FS_48000HZ (AK4117_FS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AK4117_FS_32000HZ (AK4117_FS1|AK4117_FS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AK4117_FS_88200HZ (AK4117_FS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AK4117_FS_96000HZ (AK4117_FS3|AK4117_FS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AK4117_FS_176400HZ (AK4117_FS3|AK4117_FS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AK4117_FS_192000HZ (AK4117_FS3|AK4117_FS2|AK4117_FS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* AK4117_REG_RCS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AK4117_CCRC (1<<1) /* CRC for channel status, 0 = no error, 1 = error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AK4117_QCRC (1<<0) /* CRC for Q-subcode, 0 = no error, 1 = error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* flags for snd_ak4117_check_rate_and_errors() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AK4117_CHECK_NO_STAT (1<<0) /* no statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AK4117_CHECK_NO_RATE (1<<1) /* no rate check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AK4117_CONTROLS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) typedef void (ak4117_write_t)(void *private_data, unsigned char addr, unsigned char data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) typedef unsigned char (ak4117_read_t)(void *private_data, unsigned char addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) AK4117_PARITY_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) AK4117_V_BIT_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) AK4117_QCRC_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) AK4117_CCRC_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) AK4117_NUM_ERRORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct ak4117 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ak4117_write_t * write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ak4117_read_t * read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void * private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int init: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned char regmap[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct snd_kcontrol *kctls[AK4117_CONTROLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long errors[AK4117_NUM_ERRORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned char rcs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned char rcs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned char rcs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct timer_list timer; /* statistic timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) void *change_callback_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void (*change_callback)(struct ak4117 *ak4117, unsigned char c0, unsigned char c1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void snd_ak4117_reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char mask, unsigned char val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void snd_ak4117_reinit(struct ak4117 *ak4117);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int snd_ak4117_external_rate(struct ak4117 *ak4117);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif /* __SOUND_AK4117_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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