Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __SOUND_AK4113_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __SOUND_AK4113_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Routines for Asahi Kasei AK4113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Copyright (c) by Pavel Hofman <pavel.hofman@ivitera.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* AK4113 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define AK4113_REG_PWRDN	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /* format control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define AK4113_REG_FORMAT	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* input/output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AK4113_REG_IO0		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* input/output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AK4113_REG_IO1		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* interrupt0 mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AK4113_REG_INT0_MASK	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* interrupt1 mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AK4113_REG_INT1_MASK	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* DAT mask & DTS select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AK4113_REG_DATDTS	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* receiver status 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AK4113_REG_RCS0		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* receiver status 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define AK4113_REG_RCS1		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* receiver status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AK4113_REG_RCS2		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* RX channel status byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define AK4113_REG_RXCSB0	0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* RX channel status byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AK4113_REG_RXCSB1	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* RX channel status byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AK4113_REG_RXCSB2	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* RX channel status byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define AK4113_REG_RXCSB3	0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* RX channel status byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define AK4113_REG_RXCSB4	0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* burst preamble Pc byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AK4113_REG_Pc0		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* burst preamble Pc byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define AK4113_REG_Pc1		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* burst preamble Pd byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define AK4113_REG_Pd0		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* burst preamble Pd byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AK4113_REG_Pd1		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Q-subcode address + control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define AK4113_REG_QSUB_ADDR	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* Q-subcode track */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AK4113_REG_QSUB_TRACK	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* Q-subcode index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AK4113_REG_QSUB_INDEX	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* Q-subcode minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define AK4113_REG_QSUB_MINUTE	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* Q-subcode second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define AK4113_REG_QSUB_SECOND	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* Q-subcode frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AK4113_REG_QSUB_FRAME	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* Q-subcode zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AK4113_REG_QSUB_ZERO	0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* Q-subcode absolute minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AK4113_REG_QSUB_ABSMIN	0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* Q-subcode absolute second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define AK4113_REG_QSUB_ABSSEC	0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* Q-subcode absolute frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AK4113_REG_QSUB_ABSFRM	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define AK4113_REG_RXCSB_SIZE	((AK4113_REG_RXCSB4-AK4113_REG_RXCSB0)+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define AK4113_REG_QSUB_SIZE	((AK4113_REG_QSUB_ABSFRM-AK4113_REG_QSUB_ADDR)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define AK4113_WRITABLE_REGS	(AK4113_REG_DATDTS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* AK4113_REG_PWRDN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* Channel Status Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define AK4113_CS12		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* Block Start & C/U Output Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define AK4113_BCU		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* Master Clock Operation Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define AK4113_CM1		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* Master Clock Operation Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define AK4113_CM0		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* Master Clock Frequency Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define AK4113_OCKS1		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* Master Clock Frequency Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define AK4113_OCKS0		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) /* 0 = power down, 1 = normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define AK4113_PWN		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* 0 = reset & initialize (except thisregister), 1 = normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define AK4113_RST		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* AK4113_REQ_FORMAT bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* V/TX Output select: 0 = Validity Flag Output, 1 = TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define AK4113_VTX		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* Audio Data Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AK4113_DIF2		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Audio Data Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AK4113_DIF1		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Audio Data Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AK4113_DIF0		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Deemphasis Autodetect Enable (1 = enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AK4113_DEAU		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* 32kHz-48kHz Deemphasis Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AK4113_DEM1		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* 32kHz-48kHz Deemphasis Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AK4113_DEM0		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AK4113_DEM_OFF		(AK4113_DEM0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AK4113_DEM_44KHZ	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AK4113_DEM_48KHZ	(AK4113_DEM1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AK4113_DEM_32KHZ	(AK4113_DEM0|AK4113_DEM1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* STDO: 16-bit, right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AK4113_DIF_16R		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* STDO: 18-bit, right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AK4113_DIF_18R		(AK4113_DIF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* STDO: 20-bit, right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AK4113_DIF_20R		(AK4113_DIF1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* STDO: 24-bit, right justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AK4113_DIF_24R		(AK4113_DIF1|AK4113_DIF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* STDO: 24-bit, left justified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AK4113_DIF_24L		(AK4113_DIF2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* STDO: I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AK4113_DIF_24I2S	(AK4113_DIF2|AK4113_DIF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* STDO: 24-bit, left justified; LRCLK, BICK = Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AK4113_DIF_I24L		(AK4113_DIF2|AK4113_DIF1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* STDO: I2S;  LRCLK, BICK = Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AK4113_DIF_I24I2S	(AK4113_DIF2|AK4113_DIF1|AK4113_DIF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* AK4113_REG_IO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AK4113_XTL1		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AK4113_XTL0		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Block Start Signal Output: 0 = U-bit, 1 = C-bit (req. BCU = 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AK4113_UCE		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* TX Output Enable (1 = enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AK4113_TXE		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Output Through Data Selector for TX pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AK4113_OPS2		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Output Through Data Selector for TX pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AK4113_OPS1		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Output Through Data Selector for TX pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AK4113_OPS0		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* 11.2896 MHz ref. Xtal freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AK4113_XTL_11_2896M	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* 12.288 MHz ref. Xtal freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AK4113_XTL_12_288M	(AK4113_XTL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* 24.576 MHz ref. Xtal freq. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AK4113_XTL_24_576M	(AK4113_XTL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* AK4113_REG_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Interrupt 0 pin Hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AK4113_EFH1		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Interrupt 0 pin Hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AK4113_EFH0		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AK4113_EFH_512LRCLK	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AK4113_EFH_1024LRCLK	(AK4113_EFH0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AK4113_EFH_2048LRCLK	(AK4113_EFH1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AK4113_EFH_4096LRCLK	(AK4113_EFH1|AK4113_EFH0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AK4113_FAST		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* MCKO2 Output Select: 0 = CMx/OCKSx, 1 = Xtal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AK4113_XMCK		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* MCKO2 Output Freq. Select: 0 = x1, 1 = x0.5  (req. XMCK = 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AK4113_DIV		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Input Recovery Data Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AK4113_IPS2		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Input Recovery Data Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AK4113_IPS1		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Input Recovery Data Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AK4113_IPS0		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AK4113_IPS(x)		((x)&7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* AK4113_REG_INT0_MASK && AK4113_REG_INT1_MASK*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* mask enable for QINT bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AK4113_MQI		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* mask enable for AUTO bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AK4113_MAUT		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* mask enable for CINT bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AK4113_MCIT		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* mask enable for UNLOCK bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AK4113_MULK		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* mask enable for V bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AK4113_V		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* mask enable for STC bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AK4113_STC		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* mask enable for AUDN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AK4113_MAN		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* mask enable for PAR bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AK4113_MPR		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* AK4113_REG_DATDTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* DAT Start ID Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AK4113_DCNT		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* DTS-CD 16-bit Sync Word Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AK4113_DTS16		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* DTS-CD 14-bit Sync Word Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AK4113_DTS14		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* mask enable for DAT bit (if 1, no INT1 effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AK4113_MDAT1		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* mask enable for DAT bit (if 1, no INT0 effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AK4113_MDAT0		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* AK4113_REG_RCS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AK4113_QINT		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AK4113_AUTO		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* channel status buffer interrupt, 0 = no change, 1 = change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AK4113_CINT		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* PLL lock status, 0 = lock, 1 = unlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AK4113_UNLCK		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Validity bit, 0 = valid, 1 = invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AK4113_V		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AK4113_STC		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* audio bit output, 0 = audio, 1 = non-audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AK4113_AUDION		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* parity error or biphase error status, 0 = no error, 1 = error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AK4113_PAR		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* AK4113_REG_RCS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* sampling frequency detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AK4113_FS3		(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AK4113_FS2		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AK4113_FS1		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AK4113_FS0		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Pre-emphasis detect, 0 = OFF, 1 = ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AK4113_PEM		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* DAT Start ID Detect, 0 = no detect, 1 = detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AK4113_DAT		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AK4113_DTSCD		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AK4113_NPCM		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AK4113_FS_8000HZ	(AK4113_FS3|AK4113_FS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AK4113_FS_11025HZ	(AK4113_FS2|AK4113_FS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AK4113_FS_16000HZ	(AK4113_FS2|AK4113_FS1|AK4113_FS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define AK4113_FS_22050HZ	(AK4113_FS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AK4113_FS_24000HZ	(AK4113_FS2|AK4113_FS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AK4113_FS_32000HZ	(AK4113_FS1|AK4113_FS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AK4113_FS_44100HZ	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define AK4113_FS_48000HZ	(AK4113_FS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define AK4113_FS_64000HZ	(AK4113_FS3|AK4113_FS1|AK4113_FS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define AK4113_FS_88200HZ	(AK4113_FS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define AK4113_FS_96000HZ	(AK4113_FS3|AK4113_FS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AK4113_FS_176400HZ	(AK4113_FS3|AK4113_FS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AK4113_FS_192000HZ	(AK4113_FS3|AK4113_FS2|AK4113_FS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* AK4113_REG_RCS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* CRC for Q-subcode, 0 = no error, 1 = error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AK4113_QCRC		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* CRC for channel status, 0 = no error, 1 = error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AK4113_CCRC		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* flags for snd_ak4113_check_rate_and_errors() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define AK4113_CHECK_NO_STAT	(1<<0)	/* no statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AK4113_CHECK_NO_RATE	(1<<1)	/* no rate check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AK4113_CONTROLS		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) typedef void (ak4113_write_t)(void *private_data, unsigned char addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		unsigned char data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) typedef unsigned char (ak4113_read_t)(void *private_data, unsigned char addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	AK4113_PARITY_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	AK4113_V_BIT_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	AK4113_QCRC_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	AK4113_CCRC_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	AK4113_NUM_ERRORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct ak4113 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	ak4113_write_t *write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	ak4113_read_t *read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	atomic_t wq_processing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct mutex reinit_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	unsigned char regmap[AK4113_WRITABLE_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	struct snd_kcontrol *kctls[AK4113_CONTROLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	unsigned long errors[AK4113_NUM_ERRORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	unsigned char rcs0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	unsigned char rcs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	unsigned char rcs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct delayed_work work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	unsigned int check_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	void *change_callback_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	void (*change_callback)(struct ak4113 *ak4113, unsigned char c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			unsigned char c1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		ak4113_write_t *write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		const unsigned char *pgm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		void *private_data, struct ak4113 **r_ak4113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void snd_ak4113_reg_write(struct ak4113 *ak4113, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		unsigned char mask, unsigned char val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void snd_ak4113_reinit(struct ak4113 *ak4113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int snd_ak4113_build(struct ak4113 *ak4113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		struct snd_pcm_substream *capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int snd_ak4113_external_rate(struct ak4113 *ak4113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void snd_ak4113_suspend(struct ak4113 *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void snd_ak4113_resume(struct ak4113 *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static inline void snd_ak4113_suspend(struct ak4113 *chip) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static inline void snd_ak4113_resume(struct ak4113 *chip) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #endif /* __SOUND_AK4113_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)