^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ACI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ACI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define ACI_REG_COMMAND 0 /* write register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define ACI_REG_STATUS 1 /* read register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define ACI_REG_BUSY 2 /* busy register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define ACI_REG_RDS 2 /* PCM20: RDS register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ACI_MINTIME 500 /* ACI time out limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ACI_SET_MUTE 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ACI_SET_POWERAMP 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ACI_SET_TUNERMUTE 0xa3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ACI_SET_TUNERMONO 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ACI_SET_IDE 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ACI_SET_WSS 0xd1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ACI_SET_SOLOMODE 0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ACI_SET_PREAMP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ACI_GET_PREAMP 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ACI_WRITE_TUNE 0xa7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ACI_READ_TUNERSTEREO 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ACI_READ_TUNERSTATION 0xa9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ACI_READ_VERSION 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ACI_READ_IDCODE 0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ACI_INIT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ACI_STATUS 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ACI_S_GENERAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ACI_ERROR_OP 0xdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* ACI Mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* These are the values for the right channel GET registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Add an offset of 0x01 for the left channel register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) (left=right+0x01) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ACI_GET_MASTER 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ACI_GET_MIC 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ACI_GET_LINE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ACI_GET_CD 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ACI_GET_SYNTH 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ACI_GET_PCM 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ACI_GET_LINE1 0x10 /* Radio on PCM20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ACI_GET_LINE2 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ACI_GET_EQ1 0x22 /* from Bass ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ACI_GET_EQ2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ACI_GET_EQ3 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ACI_GET_EQ4 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ACI_GET_EQ5 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ACI_GET_EQ6 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ACI_GET_EQ7 0x2e /* ... to Treble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* And these are the values for the right channel SET registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) For left channel access you have to add an offset of 0x08.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MASTER is an exception, which needs an offset of 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ACI_SET_MASTER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ACI_SET_MIC 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ACI_SET_LINE 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ACI_SET_CD 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ACI_SET_SYNTH 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ACI_SET_PCM 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ACI_SET_LINE1 0x35 /* Radio on PCM20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ACI_SET_LINE2 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ACI_SET_EQ1 0x40 /* from Bass ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ACI_SET_EQ2 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ACI_SET_EQ3 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ACI_SET_EQ4 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ACI_SET_EQ5 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ACI_SET_EQ6 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ACI_SET_EQ7 0x46 /* ... to Treble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct snd_miro_aci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long aci_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int aci_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int aci_product;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int aci_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int aci_amp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int aci_preamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int aci_solomode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct mutex aci_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int snd_aci_cmd(struct snd_miro_aci *aci, int write1, int write2, int write3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct snd_miro_aci *snd_aci_get_aci(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif /* _ACI_H_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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