^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Universal interface for Audio Codec '97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * For more details look to AC '97 component specification revision 2.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * by Intel Corporation (http://developer.intel.com).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __SOUND_AC97_CODEC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __SOUND_AC97_CODEC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/ac97/regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* maximum number of devices on the AC97 bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AC97_BUS_MAX_DEVICES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* specific - SigmaTel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AC97_SIGMATEL_OUTSEL 0x64 /* Output Select, STAC9758 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AC97_SIGMATEL_INSEL 0x66 /* Input Select, STAC9758 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AC97_SIGMATEL_IOMISC 0x68 /* STAC9758 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AC97_SIGMATEL_ANALOG 0x6c /* Analog Special */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AC97_SIGMATEL_DAC2INVERT 0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AC97_SIGMATEL_BIAS1 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AC97_SIGMATEL_BIAS2 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AC97_SIGMATEL_VARIOUS 0x72 /* STAC9758 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AC97_SIGMATEL_MULTICHN 0x74 /* Multi-Channel programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AC97_SIGMATEL_CIC1 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AC97_SIGMATEL_CIC2 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* specific - Analog Devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AC97_AD_TEST 0x5a /* test register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AC97_AD_TEST2 0x5c /* undocumented test register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AC97_AD_HPFD_SHIFT 12 /* High Pass Filter Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AC97_AD_CODEC_CFG 0x70 /* codec configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AC97_AD_MISC 0x76 /* Misc Control Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AC97_AD_VREFD_SHIFT 2 /* V_REFOUT Disable (AD1888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* specific - Cirrus Logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AC97_CSR_ACMODE 0x5e /* AC Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AC97_CSR_MISC_CRYSTAL 0x60 /* Misc Crystal Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AC97_CSR_SPDIF 0x68 /* S/PDIF Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AC97_CSR_SERIAL 0x6a /* Serial Port Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AC97_CSR_SPECF_ADDR 0x6c /* Special Feature Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AC97_CSR_SPECF_DATA 0x6e /* Special Feature Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AC97_CSR_BDI_STATUS 0x7a /* BDI Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* specific - Conexant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AC97_CXR_AUDIO_MISC 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AC97_CXR_SPDIFEN (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AC97_CXR_COPYRGT (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AC97_CXR_SPDIF_MASK (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AC97_CXR_SPDIF_PCM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AC97_CXR_SPDIF_AC3 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* specific - ALC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AC97_ALC650_SPDIF_INPUT_STATUS1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* S/PDIF input status 1 bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AC97_ALC650_PRO 0x0001 /* Professional status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AC97_ALC650_NAUDIO 0x0002 /* Non audio stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AC97_ALC650_COPY 0x0004 /* Copyright status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AC97_ALC650_PRE 0x0038 /* Preemphasis status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AC97_ALC650_PRE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AC97_ALC650_MODE 0x00C0 /* Preemphasis status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AC97_ALC650_MODE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AC97_ALC650_CC_MASK 0x7f00 /* Category Code mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AC97_ALC650_CC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AC97_ALC650_L 0x8000 /* Generation Level status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AC97_ALC650_SPDIF_INPUT_STATUS2 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* S/PDIF input status 2 bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AC97_ALC650_SOUCE_MASK 0x000f /* Source number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AC97_ALC650_CHANNEL_MASK 0x00f0 /* Channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AC97_ALC650_CHANNEL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AC97_ALC650_SPSR_MASK 0x0f00 /* S/PDIF Sample Rate bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AC97_ALC650_SPSR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AC97_ALC650_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AC97_ALC650_SPSR_48K 0x0200 /* Use 48kHz Sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AC97_ALC650_SPSR_32K 0x0300 /* Use 32kHz Sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AC97_ALC650_CLOCK_ACCURACY 0x3000 /* Clock accuracy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AC97_ALC650_CLOCK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AC97_ALC650_CLOCK_LOCK 0x4000 /* Clock locked status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AC97_ALC650_V 0x8000 /* Validity status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AC97_ALC650_SURR_DAC_VOL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AC97_ALC650_LFE_DAC_VOL 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AC97_ALC650_UNKNOWN1 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AC97_ALC650_MULTICH 0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AC97_ALC650_UNKNOWN2 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AC97_ALC650_REVISION 0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AC97_ALC650_UNKNOWN3 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AC97_ALC650_UNKNOWN4 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AC97_ALC650_MISC 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AC97_ALC650_GPIO_SETUP 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AC97_ALC650_GPIO_STATUS 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AC97_ALC650_CLOCK 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* specific - Yamaha YMF7x3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AC97_YMF7X3_DIT_CTRL 0x66 /* DIT Control (YMF743) / 2 (YMF753) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AC97_YMF7X3_3D_MODE_SEL 0x68 /* 3D Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* specific - C-Media */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AC97_CM9738_VENDOR_CTRL 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AC97_CM9739_MULTI_CHAN 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AC97_CM9739_SPDIF_IN_STATUS 0x68 /* 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AC97_CM9739_SPDIF_CTRL 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* specific - wolfson */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AC97_WM97XX_FMIXER_VOL 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AC97_WM9704_RMIXER_VOL 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AC97_WM9704_TEST 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AC97_WM9704_RPCM_VOL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AC97_WM9711_OUT3VOL 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* ac97->scaps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AC97_SCAP_AUDIO (1<<0) /* audio codec 97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AC97_SCAP_MODEM (1<<1) /* modem codec 97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AC97_SCAP_SURROUND_DAC (1<<2) /* surround L&R DACs are present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AC97_SCAP_CENTER_LFE_DAC (1<<3) /* center and LFE DACs are present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AC97_SCAP_SKIP_AUDIO (1<<4) /* skip audio part of codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AC97_SCAP_SKIP_MODEM (1<<5) /* skip modem part of codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AC97_SCAP_INDEP_SDIN (1<<6) /* independent SDIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AC97_SCAP_INV_EAPD (1<<7) /* inverted EAPD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AC97_SCAP_DETECT_BY_VENDOR (1<<8) /* use vendor registers for read tests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AC97_SCAP_NO_SPDIF (1<<9) /* don't build SPDIF controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AC97_SCAP_EAPD_LED (1<<10) /* EAPD as mute LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AC97_SCAP_POWER_SAVE (1<<11) /* capable for aggressive power-saving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* ac97->flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AC97_HAS_PC_BEEP (1<<0) /* force PC Speaker usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AC97_AD_MULTI (1<<1) /* Analog Devices - multi codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AC97_CS_SPDIF (1<<2) /* Cirrus Logic uses funky SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AC97_CX_SPDIF (1<<3) /* Conexant's spdif interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AC97_STEREO_MUTES (1<<4) /* has stereo mute bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AC97_DOUBLE_RATE (1<<5) /* supports double rate playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AC97_HAS_NO_MASTER_VOL (1<<6) /* no Master volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AC97_HAS_NO_PCM_VOL (1<<7) /* no PCM volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AC97_DEFAULT_POWER_OFF (1<<8) /* no RESET write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AC97_MODEM_PATCH (1<<9) /* modem patch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AC97_HAS_NO_REC_GAIN (1<<10) /* no Record gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AC97_HAS_NO_PHONE (1<<11) /* no PHONE volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AC97_HAS_NO_PC_BEEP (1<<12) /* no PC Beep volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AC97_HAS_NO_VIDEO (1<<13) /* no Video volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AC97_HAS_NO_CD (1<<14) /* no CD volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AC97_HAS_NO_MIC (1<<15) /* no MIC volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AC97_HAS_NO_TONE (1<<16) /* no Tone volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AC97_HAS_NO_STD_PCM (1<<17) /* no standard AC97 PCM volume and mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AC97_HAS_NO_AUX (1<<18) /* no standard AC97 AUX volume and mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AC97_HAS_8CH (1<<19) /* supports 8-channel output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* rates indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AC97_RATES_FRONT_DAC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AC97_RATES_SURR_DAC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AC97_RATES_LFE_DAC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AC97_RATES_ADC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AC97_RATES_MIC_ADC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AC97_RATES_SPDIF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AC97_NUM_GPIOS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct snd_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct snd_ac97_gpio_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct snd_pcm_chmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct snd_ac97_build_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int (*build_3d) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int (*build_specific) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int (*build_spdif) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int (*build_post_spdif) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void (*suspend) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void (*resume) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void (*update_jacks) (struct snd_ac97 *ac97); /* for jack-sharing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct snd_ac97_bus_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void (*reset) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void (*warm_reset)(struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void (*write) (struct snd_ac97 *ac97, unsigned short reg, unsigned short val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned short (*read) (struct snd_ac97 *ac97, unsigned short reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void (*wait) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void (*init) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct snd_ac97_bus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* -- lowlevel (hardware) driver specific -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) const struct snd_ac97_bus_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) void (*private_free) (struct snd_ac97_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned short num; /* bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned short no_vra: 1, /* bridge doesn't support VRA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dra: 1, /* bridge supports double rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) isdin: 1;/* independent SDIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int clock; /* AC'97 base clock (usually 48000Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spinlock_t bus_lock; /* used mainly for slot allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned short used_slots[2][4]; /* actually used PCM slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned short pcms_count; /* count of PCMs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct ac97_pcm *pcms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct snd_ac97 *codec[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct snd_info_entry *proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* static resolution table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct snd_ac97_res_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned short reg; /* register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned short bits; /* resolution bitmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct snd_ac97_template {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void (*private_free) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct pci_dev *pci; /* assigned PCI device - used for quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned short addr; /* physical address of codec [0-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned int scaps; /* driver capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) const struct snd_ac97_res_table *res_table; /* static resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct snd_ac97 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* -- lowlevel (hardware) driver specific -- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const struct snd_ac97_build_ops *build_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void *private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void (*private_free) (struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct snd_ac97_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct pci_dev *pci; /* assigned PCI device - used for quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct snd_info_entry *proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct snd_info_entry *proc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned short subsystem_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned short subsystem_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct mutex reg_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct mutex page_mutex; /* mutex for AD18xx multi-codecs and paging (2.3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned short addr; /* physical address of codec [0-3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned int id; /* identification of codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned short caps; /* capabilities (register 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned short ext_id; /* extended feature identification (register 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned short ext_mid; /* extended modem ID (register 3C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) const struct snd_ac97_res_table *res_table; /* static resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int scaps; /* driver capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned int flags; /* specific code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int rates[6]; /* see AC97_RATES_* defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int spdif_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned short regs[0x80]; /* register cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) union { /* vendor specific code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned short unchained[3]; // 0 = C34, 1 = C79, 2 = C69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned short chained[3]; // 0 = C34, 1 = C79, 2 = C69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned short id[3]; // codec IDs (lower 16-bit word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned short pcmreg[3]; // PCM registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned short codec_cfg[3]; // CODEC_CFG bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned char swap_mic_linein; // AD1986/AD1986A only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned char lo_as_master; /* LO as master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } ad18xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int dev_flags; /* device specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* jack-sharing info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned char indep_surround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned char channel_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #ifdef CONFIG_SND_AC97_POWER_SAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int power_up; /* power states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct delayed_work power_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct snd_ac97_gpio_priv *gpio_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct snd_pcm_chmap *chmaps[2]; /* channel-maps (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define to_ac97_t(d) container_of(d, struct snd_ac97, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static inline int ac97_is_audio(struct snd_ac97 * ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return (ac97->scaps & AC97_SCAP_AUDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static inline int ac97_is_modem(struct snd_ac97 * ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return (ac97->scaps & AC97_SCAP_MODEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline int ac97_is_rev22(struct snd_ac97 * ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return (ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static inline int ac97_can_amap(struct snd_ac97 * ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return (ac97->ext_id & AC97_EI_AMAP) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static inline int ac97_can_spdif(struct snd_ac97 * ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return (ac97->ext_id & AC97_EI_SPDIF) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* create new AC97 bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int snd_ac97_bus(struct snd_card *card, int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const struct snd_ac97_bus_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void *private_data, struct snd_ac97_bus **rbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* create mixer controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int snd_ac97_mixer(struct snd_ac97_bus *bus, struct snd_ac97_template *template,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct snd_ac97 **rac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) const char *snd_ac97_get_short_name(struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void snd_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned short snd_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void snd_ac97_write_cache(struct snd_ac97 *ac97, unsigned short reg, unsigned short value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int snd_ac97_update(struct snd_ac97 *ac97, unsigned short reg, unsigned short value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int snd_ac97_update_bits(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #ifdef CONFIG_SND_AC97_POWER_SAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, int powerup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static inline int snd_ac97_update_power(struct snd_ac97 *ac97, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int powerup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) void snd_ac97_suspend(struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) void snd_ac97_resume(struct snd_ac97 *ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int snd_ac97_reset(struct snd_ac97 *ac97, bool try_warm, unsigned int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int id_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* quirk types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) AC97_TUNE_DEFAULT = -1, /* use default from quirk list (not valid in list) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) AC97_TUNE_NONE = 0, /* nothing extra to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) AC97_TUNE_HP_ONLY, /* headphone (true line-out) control as master only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) AC97_TUNE_SWAP_HP, /* swap headphone and master controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) AC97_TUNE_SWAP_SURROUND, /* swap master and surround controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) AC97_TUNE_AD_SHARING, /* for AD1985, turn on OMS bit and use headphone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) AC97_TUNE_ALC_JACK, /* for Realtek, enable JACK detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) AC97_TUNE_INV_EAPD, /* inverted EAPD implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) AC97_TUNE_MUTE_LED, /* EAPD bit works as mute LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) AC97_TUNE_HP_MUTE_LED, /* EAPD bit works as mute LED, use headphone control as master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct ac97_quirk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned short subvendor; /* PCI subsystem vendor id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned short subdevice; /* PCI subsystem device id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned short mask; /* device id bit mask, 0 = accept all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int codec_id; /* codec id (if any), 0 = accept all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) const char *name; /* name shown as info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int type; /* quirk type above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int snd_ac97_tune_hardware(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) const struct ac97_quirk *quirk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) const char *override);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int snd_ac97_set_rate(struct snd_ac97 *ac97, int reg, unsigned int rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * PCM allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) enum ac97_pcm_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) AC97_PCM_CFG_FRONT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) AC97_PCM_CFG_REAR = 10, /* alias surround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) AC97_PCM_CFG_LFE = 11, /* center + lfe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) AC97_PCM_CFG_40 = 4, /* front + rear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) AC97_PCM_CFG_51 = 6, /* front + rear + center/lfe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) AC97_PCM_CFG_SPDIF = 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct ac97_pcm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct snd_ac97_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int stream: 1, /* stream type: 1 = capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) exclusive: 1, /* exclusive mode, don't override with other pcms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) copy_flag: 1, /* lowlevel driver must fill all entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) spdif: 1; /* spdif pcm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned short aslots; /* active slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned short cur_dbl; /* current double-rate state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int rates; /* available rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned short slots; /* driver input: requested AC97 slot numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned short rslots[4]; /* allocated slots per codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned char rate_table[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct snd_ac97 *codec[4]; /* allocated codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } r[2]; /* 0 = standard rates, 1 = double rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned long private_value; /* used by the hardware driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int snd_ac97_pcm_assign(struct snd_ac97_bus *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned short pcms_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) const struct ac97_pcm *pcms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int snd_ac97_pcm_open(struct ac97_pcm *pcm, unsigned int rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) enum ac97_pcm_cfg cfg, unsigned short slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int snd_ac97_pcm_close(struct ac97_pcm *pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int snd_ac97_pcm_double_rate_rules(struct snd_pcm_runtime *runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* ad hoc AC97 device driver access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) extern struct bus_type ac97_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* AC97 platform_data adding function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static inline void snd_ac97_dev_add_pdata(struct snd_ac97 *ac97, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ac97->dev.platform_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #endif /* __SOUND_AC97_CODEC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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