^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Universal interface for Audio Codec '97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * For more details look to AC '97 component specification revision 2.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * by Intel Corporation (http://developer.intel.com).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * AC'97 codec registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AC97_RESET 0x00 /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AC97_MASTER 0x02 /* Master Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AC97_PC_BEEP 0x0a /* PC Beep Volume (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AC97_PHONE 0x0c /* Phone Volume (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AC97_MIC 0x0e /* MIC Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AC97_LINE 0x10 /* Line In Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AC97_CD 0x12 /* CD Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AC97_VIDEO 0x14 /* Video Volume (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AC97_AUX 0x16 /* AUX Volume (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AC97_PCM 0x18 /* PCM Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AC97_REC_SEL 0x1a /* Record Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AC97_REC_GAIN 0x1c /* Record Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AC97_REC_GAIN_MIC 0x1e /* Record Gain MIC (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AC97_GENERAL_PURPOSE 0x20 /* General Purpose (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AC97_3D_CONTROL 0x22 /* 3D Control (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AC97_INT_PAGING 0x24 /* Audio Interrupt & Paging (AC'97 2.3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AC97_POWERDOWN 0x26 /* Powerdown control / status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AC97_EXTENDED_ID 0x28 /* Extended Audio ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AC97_EXTENDED_STATUS 0x2a /* Extended Audio Status and Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AC97_CENTER_LFE_MASTER 0x36 /* Center + LFE Master Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AC97_SURROUND_MASTER 0x38 /* Surround (Rear) Master Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AC97_SPDIF 0x3a /* S/PDIF control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* range 0x3c-0x58 - MODEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AC97_EXTENDED_MID 0x3c /* Extended Modem ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AC97_EXTENDED_MSTATUS 0x3e /* Extended Modem Status and Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AC97_LINE1_RATE 0x40 /* Line1 DAC/ADC Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AC97_LINE2_RATE 0x42 /* Line2 DAC/ADC Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AC97_HANDSET_RATE 0x44 /* Handset DAC/ADC Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AC97_LINE1_LEVEL 0x46 /* Line1 DAC/ADC Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AC97_LINE2_LEVEL 0x48 /* Line2 DAC/ADC Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AC97_HANDSET_LEVEL 0x4a /* Handset DAC/ADC Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AC97_GPIO_CFG 0x4c /* GPIO Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AC97_GPIO_POLARITY 0x4e /* GPIO Pin Polarity/Type, 0=low, 1=high active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AC97_GPIO_STICKY 0x50 /* GPIO Pin Sticky, 0=not, 1=sticky */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AC97_GPIO_WAKEUP 0x52 /* GPIO Pin Wakeup, 0=no int, 1=yes int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AC97_GPIO_STATUS 0x54 /* GPIO Pin Status, slot 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AC97_MISC_AFE 0x56 /* Miscellaneous Modem AFE Status and Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* range 0x5a-0x7b - Vendor Specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AC97_VENDOR_ID1 0x7c /* Vendor ID1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AC97_VENDOR_ID2 0x7e /* Vendor ID2 / revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* range 0x60-0x6f (page 1) - extended codec registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AC97_CODEC_CLASS_REV 0x60 /* Codec Class/Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AC97_PCI_SVID 0x62 /* PCI Subsystem Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AC97_PCI_SID 0x64 /* PCI Subsystem ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AC97_FUNC_SELECT 0x66 /* Function Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AC97_FUNC_INFO 0x68 /* Function Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AC97_SENSE_INFO 0x6a /* Sense Details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* volume controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AC97_MUTE_MASK_MONO 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AC97_MUTE_MASK_STEREO 0x8080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* slot allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AC97_SLOT_TAG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AC97_SLOT_CMD_ADDR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AC97_SLOT_CMD_DATA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AC97_SLOT_PCM_LEFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AC97_SLOT_PCM_RIGHT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AC97_SLOT_MODEM_LINE1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AC97_SLOT_PCM_CENTER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AC97_SLOT_MIC 6 /* input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AC97_SLOT_SPDIF_LEFT1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AC97_SLOT_PCM_SLEFT 7 /* surround left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AC97_SLOT_PCM_LEFT_0 7 /* double rate operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AC97_SLOT_SPDIF_LEFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define AC97_SLOT_PCM_SRIGHT 8 /* surround right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AC97_SLOT_PCM_RIGHT_0 8 /* double rate operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AC97_SLOT_SPDIF_RIGHT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AC97_SLOT_LFE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AC97_SLOT_SPDIF_RIGHT1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define AC97_SLOT_MODEM_LINE2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AC97_SLOT_PCM_LEFT_1 10 /* double rate operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define AC97_SLOT_SPDIF_LEFT2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AC97_SLOT_HANDSET 11 /* output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AC97_SLOT_PCM_RIGHT_1 11 /* double rate operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AC97_SLOT_SPDIF_RIGHT2 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AC97_SLOT_MODEM_GPIO 12 /* modem GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AC97_SLOT_PCM_CENTER_1 12 /* double rate operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* basic capabilities (reset register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AC97_BC_DEDICATED_MIC 0x0001 /* Dedicated Mic PCM In Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AC97_BC_RESERVED1 0x0002 /* Reserved (was Modem Line Codec support) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AC97_BC_BASS_TREBLE 0x0004 /* Bass & Treble Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AC97_BC_SIM_STEREO 0x0008 /* Simulated stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AC97_BC_HEADPHONE 0x0010 /* Headphone Out Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AC97_BC_LOUDNESS 0x0020 /* Loudness (bass boost) Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AC97_BC_16BIT_DAC 0x0000 /* 16-bit DAC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AC97_BC_18BIT_DAC 0x0040 /* 18-bit DAC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AC97_BC_20BIT_DAC 0x0080 /* 20-bit DAC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AC97_BC_DAC_MASK 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AC97_BC_16BIT_ADC 0x0000 /* 16-bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AC97_BC_18BIT_ADC 0x0100 /* 18-bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AC97_BC_20BIT_ADC 0x0200 /* 20-bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AC97_BC_ADC_MASK 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AC97_BC_3D_TECH_ID_MASK 0x7c00 /* Per-vendor ID of 3D enhancement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* general purpose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AC97_GP_DRSS_MASK 0x0c00 /* double rate slot select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AC97_GP_DRSS_1011 0x0000 /* LR(C) 10+11(+12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AC97_GP_DRSS_78 0x0400 /* LR 7+8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* powerdown bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AC97_PD_ADC_STATUS 0x0001 /* ADC status (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AC97_PD_DAC_STATUS 0x0002 /* DAC status (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AC97_PD_MIXER_STATUS 0x0004 /* Analog mixer status (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AC97_PD_VREF_STATUS 0x0008 /* Vref status (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AC97_PD_PR0 0x0100 /* Power down PCM ADCs and input MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AC97_PD_PR1 0x0200 /* Power down PCM front DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AC97_PD_PR2 0x0400 /* Power down Mixer (Vref still on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AC97_PD_PR3 0x0800 /* Power down Mixer (Vref off) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AC97_PD_PR4 0x1000 /* Power down AC-Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AC97_PD_PR5 0x2000 /* Disable internal clock usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AC97_PD_PR6 0x4000 /* Headphone amplifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AC97_PD_EAPD 0x8000 /* External Amplifer Power Down (EAPD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* extended audio ID bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AC97_EI_VRA 0x0001 /* Variable bit rate supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AC97_EI_DRA 0x0002 /* Double rate supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AC97_EI_SPDIF 0x0004 /* S/PDIF out supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AC97_EI_VRM 0x0008 /* Variable bit rate supported for MIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AC97_EI_DACS_SLOT_MASK 0x0030 /* DACs slot assignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AC97_EI_DACS_SLOT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AC97_EI_CDAC 0x0040 /* PCM Center DAC available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AC97_EI_SDAC 0x0080 /* PCM Surround DACs available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AC97_EI_LDAC 0x0100 /* PCM LFE DAC available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AC97_EI_AMAP 0x0200 /* indicates optional slot/DAC mapping based on codec ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AC97_EI_REV_MASK 0x0c00 /* AC'97 revision mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AC97_EI_REV_22 0x0400 /* AC'97 revision 2.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AC97_EI_REV_23 0x0800 /* AC'97 revision 2.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AC97_EI_REV_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AC97_EI_ADDR_MASK 0xc000 /* physical codec ID (address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AC97_EI_ADDR_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* extended audio status and control bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AC97_EA_VRA 0x0001 /* Variable bit rate enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AC97_EA_DRA 0x0002 /* Double-rate audio enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AC97_EA_SPDIF 0x0004 /* S/PDIF out enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AC97_EA_VRM 0x0008 /* Variable bit rate for MIC enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AC97_EA_SPSA_SLOT_MASK 0x0030 /* Mask for slot assignment bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AC97_EA_SPSA_SLOT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AC97_EA_SPSA_3_4 0x0000 /* Slot assigned to 3 & 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define AC97_EA_SPSA_7_8 0x0010 /* Slot assigned to 7 & 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AC97_EA_SPSA_6_9 0x0020 /* Slot assigned to 6 & 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AC97_EA_SPSA_10_11 0x0030 /* Slot assigned to 10 & 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AC97_EA_CDAC 0x0040 /* PCM Center DAC is ready (Read only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define AC97_EA_SDAC 0x0080 /* PCM Surround DACs are ready (Read only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AC97_EA_LDAC 0x0100 /* PCM LFE DAC is ready (Read only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AC97_EA_MDAC 0x0200 /* MIC ADC is ready (Read only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AC97_EA_SPCV 0x0400 /* S/PDIF configuration valid (Read only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define AC97_EA_PRI 0x0800 /* Turns the PCM Center DAC off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AC97_EA_PRJ 0x1000 /* Turns the PCM Surround DACs off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AC97_EA_PRK 0x2000 /* Turns the PCM LFE DAC off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AC97_EA_PRL 0x4000 /* Turns the MIC ADC off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* S/PDIF control bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AC97_SC_PRO 0x0001 /* Professional status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AC97_SC_NAUDIO 0x0002 /* Non audio stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AC97_SC_COPY 0x0004 /* Copyright status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AC97_SC_PRE 0x0008 /* Preemphasis status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AC97_SC_CC_MASK 0x07f0 /* Category Code mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AC97_SC_CC_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define AC97_SC_L 0x0800 /* Generation Level status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AC97_SC_SPSR_MASK 0x3000 /* S/PDIF Sample Rate bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AC97_SC_SPSR_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AC97_SC_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define AC97_SC_SPSR_48K 0x2000 /* Use 48kHz Sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AC97_SC_SPSR_32K 0x3000 /* Use 32kHz Sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AC97_SC_DRS 0x4000 /* Double Rate S/PDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AC97_SC_V 0x8000 /* Validity status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Interrupt and Paging bit defines (AC'97 2.3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AC97_PAGE_MASK 0x000f /* Page Selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AC97_PAGE_VENDOR 0 /* Vendor-specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AC97_PAGE_1 1 /* Extended Codec Registers page 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AC97_INT_ENABLE 0x0800 /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AC97_INT_SENSE 0x1000 /* Sense Cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AC97_INT_CAUSE_SENSE 0x2000 /* Sense Cycle Completed (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AC97_INT_CAUSE_GPIO 0x4000 /* GPIO bits changed (RO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AC97_INT_STATUS 0x8000 /* Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* extended modem ID bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AC97_MEI_LINE1 0x0001 /* Line1 present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AC97_MEI_LINE2 0x0002 /* Line2 present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AC97_MEI_HANDSET 0x0004 /* Handset present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AC97_MEI_CID1 0x0008 /* caller ID decode for Line1 is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AC97_MEI_CID2 0x0010 /* caller ID decode for Line2 is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AC97_MEI_ADDR_MASK 0xc000 /* physical codec ID (address) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AC97_MEI_ADDR_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* extended modem status and control bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AC97_MEA_GPIO 0x0001 /* GPIO is ready (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AC97_MEA_MREF 0x0002 /* Vref is up to nominal level (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AC97_MEA_ADC1 0x0004 /* ADC1 operational (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AC97_MEA_DAC1 0x0008 /* DAC1 operational (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AC97_MEA_ADC2 0x0010 /* ADC2 operational (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AC97_MEA_DAC2 0x0020 /* DAC2 operational (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AC97_MEA_HADC 0x0040 /* HADC operational (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AC97_MEA_HDAC 0x0080 /* HDAC operational (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AC97_MEA_PRA 0x0100 /* GPIO power down (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AC97_MEA_PRB 0x0200 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AC97_MEA_PRC 0x0400 /* ADC1 power down (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AC97_MEA_PRD 0x0800 /* DAC1 power down (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AC97_MEA_PRE 0x1000 /* ADC2 power down (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AC97_MEA_PRF 0x2000 /* DAC2 power down (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define AC97_MEA_PRG 0x4000 /* HADC power down (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AC97_MEA_PRH 0x8000 /* HDAC power down (high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* modem gpio status defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AC97_GPIO_LINE1_OH 0x0001 /* Off Hook Line1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define AC97_GPIO_LINE1_RI 0x0002 /* Ring Detect Line1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AC97_GPIO_LINE1_CID 0x0004 /* Caller ID path enable Line1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AC97_GPIO_LINE1_LCS 0x0008 /* Loop Current Sense Line1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AC97_GPIO_LINE1_PULSE 0x0010 /* Opt./ Pulse Dial Line1 (out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AC97_GPIO_LINE1_HL1R 0x0020 /* Opt./ Handset to Line1 relay control (out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define AC97_GPIO_LINE1_HOHD 0x0040 /* Opt./ Handset off hook detect Line1 (in) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AC97_GPIO_LINE12_AC 0x0080 /* Opt./ Int.bit 1 / Line1/2 AC (out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AC97_GPIO_LINE12_DC 0x0100 /* Opt./ Int.bit 2 / Line1/2 DC (out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AC97_GPIO_LINE12_RS 0x0200 /* Opt./ Int.bit 3 / Line1/2 RS (out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AC97_GPIO_LINE2_OH 0x0400 /* Off Hook Line2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AC97_GPIO_LINE2_RI 0x0800 /* Ring Detect Line2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define AC97_GPIO_LINE2_CID 0x1000 /* Caller ID path enable Line2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AC97_GPIO_LINE2_LCS 0x2000 /* Loop Current Sense Line2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AC97_GPIO_LINE2_PULSE 0x4000 /* Opt./ Pulse Dial Line2 (out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AC97_GPIO_LINE2_HL1R 0x8000 /* Opt./ Handset to Line2 relay control (out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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