Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2010 Google, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2014 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Colin Cross <ccross@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef __SOC_TEGRA_PMC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define __SOC_TEGRA_PMC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <soc/tegra/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) struct clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct reset_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) int tegra_pmc_cpu_power_on(unsigned int cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * powergate and I/O rail APIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TEGRA_POWERGATE_CPU	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TEGRA_POWERGATE_3D	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TEGRA_POWERGATE_VENC	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TEGRA_POWERGATE_PCIE	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TEGRA_POWERGATE_VDEC	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TEGRA_POWERGATE_L2	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TEGRA_POWERGATE_MPE	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TEGRA_POWERGATE_HEG	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TEGRA_POWERGATE_SATA	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TEGRA_POWERGATE_CPU1	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TEGRA_POWERGATE_CPU2	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TEGRA_POWERGATE_CPU3	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TEGRA_POWERGATE_CELP	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TEGRA_POWERGATE_3D1	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TEGRA_POWERGATE_CPU0	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TEGRA_POWERGATE_C0NC	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TEGRA_POWERGATE_C1NC	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TEGRA_POWERGATE_SOR	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TEGRA_POWERGATE_DIS	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TEGRA_POWERGATE_DISB	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TEGRA_POWERGATE_XUSBA	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TEGRA_POWERGATE_XUSBB	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TEGRA_POWERGATE_XUSBC	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TEGRA_POWERGATE_VIC	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TEGRA_POWERGATE_IRAM	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TEGRA_POWERGATE_NVDEC	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TEGRA_POWERGATE_NVJPG	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TEGRA_POWERGATE_AUD	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TEGRA_POWERGATE_DFD	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TEGRA_POWERGATE_VE2	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define TEGRA_POWERGATE_MAX	TEGRA_POWERGATE_VE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TEGRA_POWERGATE_3D0	TEGRA_POWERGATE_3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * enum tegra_io_pad - I/O pad group identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * can be used to control the common voltage signal level and power state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * the pins of the given pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) enum tegra_io_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	TEGRA_IO_PAD_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	TEGRA_IO_PAD_AUDIO_HV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	TEGRA_IO_PAD_BB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	TEGRA_IO_PAD_CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	TEGRA_IO_PAD_COMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	TEGRA_IO_PAD_CONN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	TEGRA_IO_PAD_CSIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	TEGRA_IO_PAD_CSIB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	TEGRA_IO_PAD_CSIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	TEGRA_IO_PAD_CSID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	TEGRA_IO_PAD_CSIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	TEGRA_IO_PAD_CSIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	TEGRA_IO_PAD_CSIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	TEGRA_IO_PAD_CSIH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	TEGRA_IO_PAD_DAP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	TEGRA_IO_PAD_DAP5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	TEGRA_IO_PAD_DBG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	TEGRA_IO_PAD_DEBUG_NONAO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	TEGRA_IO_PAD_DMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	TEGRA_IO_PAD_DMIC_HV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	TEGRA_IO_PAD_DP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	TEGRA_IO_PAD_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	TEGRA_IO_PAD_DSIB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	TEGRA_IO_PAD_DSIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	TEGRA_IO_PAD_DSID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	TEGRA_IO_PAD_EDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	TEGRA_IO_PAD_EMMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	TEGRA_IO_PAD_EMMC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	TEGRA_IO_PAD_EQOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	TEGRA_IO_PAD_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	TEGRA_IO_PAD_GP_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	TEGRA_IO_PAD_GP_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	TEGRA_IO_PAD_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	TEGRA_IO_PAD_HDMI_DP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	TEGRA_IO_PAD_HDMI_DP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	TEGRA_IO_PAD_HDMI_DP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	TEGRA_IO_PAD_HDMI_DP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	TEGRA_IO_PAD_HSIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	TEGRA_IO_PAD_HV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	TEGRA_IO_PAD_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	TEGRA_IO_PAD_MIPI_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	TEGRA_IO_PAD_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	TEGRA_IO_PAD_PEX_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	TEGRA_IO_PAD_PEX_CLK_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	TEGRA_IO_PAD_PEX_CLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	TEGRA_IO_PAD_PEX_CLK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	TEGRA_IO_PAD_PEX_CLK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	TEGRA_IO_PAD_PEX_CLK_2_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	TEGRA_IO_PAD_PEX_CLK_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	TEGRA_IO_PAD_PEX_CNTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	TEGRA_IO_PAD_PEX_CTL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	TEGRA_IO_PAD_PEX_L0_RST_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	TEGRA_IO_PAD_PEX_L1_RST_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	TEGRA_IO_PAD_PEX_L5_RST_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	TEGRA_IO_PAD_PWR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	TEGRA_IO_PAD_SDMMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	TEGRA_IO_PAD_SDMMC1_HV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	TEGRA_IO_PAD_SDMMC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	TEGRA_IO_PAD_SDMMC2_HV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	TEGRA_IO_PAD_SDMMC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	TEGRA_IO_PAD_SDMMC3_HV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	TEGRA_IO_PAD_SDMMC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	TEGRA_IO_PAD_SOC_GPIO10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	TEGRA_IO_PAD_SOC_GPIO12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	TEGRA_IO_PAD_SOC_GPIO13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	TEGRA_IO_PAD_SOC_GPIO53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	TEGRA_IO_PAD_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	TEGRA_IO_PAD_SPI_HV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	TEGRA_IO_PAD_SYS_DDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	TEGRA_IO_PAD_UART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	TEGRA_IO_PAD_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	TEGRA_IO_PAD_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	TEGRA_IO_PAD_UFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	TEGRA_IO_PAD_USB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	TEGRA_IO_PAD_USB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	TEGRA_IO_PAD_USB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	TEGRA_IO_PAD_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	TEGRA_IO_PAD_USB_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	TEGRA_IO_PAD_AO_HV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* deprecated, use TEGRA_IO_PAD_{HDMI,LVDS} instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA_IO_RAIL_HDMI	TEGRA_IO_PAD_HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA_IO_RAIL_LVDS	TEGRA_IO_PAD_LVDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #ifdef CONFIG_SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int tegra_powergate_power_on(unsigned int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int tegra_powergate_power_off(unsigned int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int tegra_powergate_remove_clamping(unsigned int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Must be called with clk disabled, and returns with clk enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				      struct reset_control *rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int tegra_io_pad_power_enable(enum tegra_io_pad id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int tegra_io_pad_power_disable(enum tegra_io_pad id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int tegra_io_rail_power_on(unsigned int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int tegra_io_rail_power_off(unsigned int id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline int tegra_powergate_power_on(unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static inline int tegra_powergate_power_off(unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline int tegra_powergate_remove_clamping(unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline int tegra_powergate_sequence_power_up(unsigned int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 						    struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 						    struct reset_control *rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline int tegra_io_pad_power_enable(enum tegra_io_pad id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline int tegra_io_pad_power_disable(enum tegra_io_pad id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline int tegra_io_pad_get_voltage(enum tegra_io_pad id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline int tegra_io_rail_power_on(unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline int tegra_io_rail_power_off(unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #endif /* CONFIG_SOC_TEGRA_PMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #if defined(CONFIG_SOC_TEGRA_PMC) && defined(CONFIG_PM_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static inline enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return TEGRA_SUSPEND_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif /* __SOC_TEGRA_PMC_H__ */