^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __SOC_TEGRA_MC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __SOC_TEGRA_MC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct tegra_smmu_enable {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct tegra_mc_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 *emem_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* latency allowance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct tegra_mc_la {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct tegra_mc_client {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int swgroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int fifo_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct tegra_smmu_enable smmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct tegra_mc_la la;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct tegra_smmu_swgroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int swgroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct tegra_smmu_group_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const unsigned int *swgroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int num_swgroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct tegra_smmu_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct tegra_mc_client *clients;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int num_clients;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) const struct tegra_smmu_swgroup *swgroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int num_swgroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const struct tegra_smmu_group_soc *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bool supports_round_robin_arbitration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bool supports_request_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int num_tlb_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int num_asids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct tegra_mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct tegra_smmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct gart_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifdef CONFIG_TEGRA_IOMMU_SMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct tegra_smmu *tegra_smmu_probe(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const struct tegra_smmu_soc *soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct tegra_mc *mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void tegra_smmu_remove(struct tegra_smmu *smmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline struct tegra_smmu *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct tegra_mc *mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef CONFIG_TEGRA_IOMMU_GART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int tegra_gart_suspend(struct gart_device *gart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int tegra_gart_resume(struct gart_device *gart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline struct gart_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline int tegra_gart_suspend(struct gart_device *gart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline int tegra_gart_resume(struct gart_device *gart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct tegra_mc_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct tegra_mc_reset_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int (*hotreset_assert)(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const struct tegra_mc_reset *rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int (*hotreset_deassert)(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const struct tegra_mc_reset *rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int (*block_dma)(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const struct tegra_mc_reset *rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool (*dma_idling)(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct tegra_mc_reset *rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int (*unblock_dma)(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct tegra_mc_reset *rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int (*reset_status)(struct tegra_mc *mc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const struct tegra_mc_reset *rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct tegra_mc_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct tegra_mc_client *clients;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int num_clients;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const unsigned long *emem_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int num_emem_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int num_address_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int atom_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 client_id_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct tegra_smmu_soc *smmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const struct tegra_mc_reset_ops *reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const struct tegra_mc_reset *resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct tegra_mc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct tegra_smmu *smmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct gart_device *gart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const struct tegra_mc_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct tegra_mc_timing *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int num_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct reset_controller_dev reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif /* __SOC_TEGRA_MC_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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