^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __TEGRA_IVC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct tegra_ivc_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct tegra_ivc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct device *peer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct tegra_ivc_header *channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned int position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) } rx, tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void (*notify)(struct tegra_ivc *ivc, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void *notify_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int num_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) size_t frame_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * tegra_ivc_read_get_next_frame - Peek at the next frame to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @ivc pointer of the IVC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Peek at the next frame to be received, without removing it from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * the queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Returns a pointer to the frame, or an error encoded pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void *tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * tegra_ivc_read_advance - Advance the read queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @ivc pointer of the IVC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Advance the read queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Returns 0, or a negative error value if failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int tegra_ivc_read_advance(struct tegra_ivc *ivc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * tegra_ivc_write_get_next_frame - Poke at the next frame to transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @ivc pointer of the IVC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Get access to the next frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Returns a pointer to the frame, or an error encoded pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) void *tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * tegra_ivc_write_advance - Advance the write queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @ivc pointer of the IVC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Advance the write queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Returns 0, or a negative error value if failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int tegra_ivc_write_advance(struct tegra_ivc *ivc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * tegra_ivc_notified - handle internal messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @ivc pointer of the IVC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * This function must be called following every notification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Returns 0 if the channel is ready for communication, or -EAGAIN if a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * reset is in progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int tegra_ivc_notified(struct tegra_ivc *ivc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * tegra_ivc_reset - initiates a reset of the shared memory state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @ivc pointer of the IVC channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * This function must be called after a channel is reserved before it is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * for communication. The channel will be ready for use when a subsequent call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * to notify the remote of the channel reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void tegra_ivc_reset(struct tegra_ivc *ivc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) size_t tegra_ivc_align(size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned tegra_ivc_total_queue_size(unsigned queue_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int tegra_ivc_init(struct tegra_ivc *ivc, struct device *peer, void *rx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dma_addr_t rx_phys, void *tx, dma_addr_t tx_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int num_frames, size_t frame_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void (*notify)(struct tegra_ivc *ivc, void *data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void tegra_ivc_cleanup(struct tegra_ivc *ivc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif /* __TEGRA_IVC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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