Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __SOC_TEGRA_FUSE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __SOC_TEGRA_FUSE_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define TEGRA20		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TEGRA30		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TEGRA114	0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TEGRA124	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA132	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA210	0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA186	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA194	0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA234	0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA_FUSE_SKU_CALIB_0	0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA30_FUSE_SATA_CALIB	0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 tegra_read_chipid(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u8 tegra_get_chip_id(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 tegra_get_platform(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) bool tegra_is_silicon(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum tegra_revision {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	TEGRA_REVISION_UNKNOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	TEGRA_REVISION_A01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	TEGRA_REVISION_A02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	TEGRA_REVISION_A03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	TEGRA_REVISION_A03p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	TEGRA_REVISION_A04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	TEGRA_REVISION_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct tegra_sku_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	int sku_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	int cpu_process_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	int cpu_speedo_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	int cpu_speedo_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	int cpu_iddq_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	int soc_process_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	int soc_speedo_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	int soc_speedo_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	int gpu_process_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	int gpu_speedo_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	int gpu_speedo_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	enum tegra_revision revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 tegra_read_straps(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 tegra_read_ram_code(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int tegra_fuse_readl(unsigned long offset, u32 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) extern struct tegra_sku_info tegra_sku_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct device *tegra_soc_device_register(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* __SOC_TEGRA_FUSE_H__ */