Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Functions and macros to control the flowcontroller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __SOC_TEGRA_FLOWCTRL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __SOC_TEGRA_FLOWCTRL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define FLOW_CTRL_HALT_CPU0_EVENTS	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define FLOW_CTRL_WAITEVENT		(2 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define FLOW_CTRL_WAIT_FOR_INTERRUPT	(4 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define FLOW_CTRL_JTAG_RESUME		(1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FLOW_CTRL_SCLK_RESUME		(1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FLOW_CTRL_HALT_CPU_IRQ		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define	FLOW_CTRL_HALT_CPU_FIQ		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FLOW_CTRL_HALT_LIC_IRQ		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FLOW_CTRL_HALT_LIC_FIQ		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FLOW_CTRL_HALT_GIC_IRQ		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FLOW_CTRL_HALT_GIC_FIQ		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FLOW_CTRL_CPU0_CSR		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define	FLOW_CTRL_CSR_INTR_FLAG		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FLOW_CTRL_CSR_EVENT_FLAG	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FLOW_CTRL_CSR_ENABLE_EXT_NCPU	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FLOW_CTRL_CSR_ENABLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FLOW_CTRL_HALT_CPU1_EVENTS	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FLOW_CTRL_CPU1_CSR		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP	(3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP	(0xF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP	(0xF << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifdef CONFIG_SOC_TEGRA_FLOWCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 flowctrl_read_cpu_csr(unsigned int cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void flowctrl_cpu_suspend_enter(unsigned int cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void flowctrl_cpu_suspend_exit(unsigned int cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif /* __ASSEMBLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif /* __SOC_TEGRA_FLOWCTRL_H__ */