^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 NVIDIA Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __SOC_TEGRA_EMC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __SOC_TEGRA_EMC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) struct tegra_emc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) void tegra_emc_complete_timing_change(struct tegra_emc *emc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #endif /* __SOC_TEGRA_EMC_H__ */